Searched refs:FA5 (Results 1 – 7 of 7) sorted by relevance
/art/runtime/arch/riscv64/ |
D | registers_riscv64.h | 95 FA5 = 15, // F15, argument 5 enumerator
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D | callee_save_frame_riscv64.h | 62 (1 << art::riscv64::FA3) | (1 << art::riscv64::FA4) | (1 << art::riscv64::FA5) | 81 (1 << art::riscv64::FA3) | (1 << art::riscv64::FA4) | (1 << art::riscv64::FA5) |
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D | context_riscv64.cc | 118 fprs_[FA5] = nullptr; in SmashCallerSaves()
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/art/compiler/utils/riscv64/ |
D | jni_macro_assembler_riscv64_test.cc | 216 __ Store(AsManaged(A3), MemberOffset(384), AsManaged(FA5), kDoubleWordSize); in TEST_F() 256 __ Load(AsManaged(FA5), AsManaged(A3), MemberOffset(384), kDoubleWordSize); in TEST_F() 459 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), kXlenInBytes), in TEST_F() 479 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), 2 * kVRegSize), in TEST_F() 537 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), kFloatSize), in TEST_F() 557 ArgumentLocation(Riscv64ManagedRegister::FromFRegister(FA5), kVRegSize), in TEST_F()
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D | assembler_riscv64_test.cc | 277 FA5, in GetFPRegisters() 315 FA5, in GetFPRegistersShort()
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/art/compiler/jni/quick/riscv64/ |
D | calling_convention_riscv64.cc | 41 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
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/art/compiler/optimizing/ |
D | code_generator_riscv64.h | 37 static constexpr FRegister kParameterFpuRegisters[] = {FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7}; 46 FA0, FA1, FA2, FA3, FA4, FA5, FA6, FA7
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