Searched refs:RA (Results 1 – 11 of 11) sorted by relevance
| /art/runtime/arch/riscv64/ |
| D | context_riscv64.cc | 47 DCHECK_NE(frame_info.CoreSpillMask() & (1u << RA), 0u); in FillCalleeSaves()
48 gprs_[RA] = CalleeSaveAddress(frame, 0, frame_info.FrameSizeInBytes()); in FillCalleeSaves()
52 for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask() & ~(1u << RA))) { in FillCalleeSaves()
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| D | registers_riscv64.h | 29 RA = 1, // X1, return address enumerator
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| D | callee_save_frame_riscv64.h | 33 (1 << art::riscv64::RA); // Return address
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| /art/compiler/utils/riscv64/ |
| D | jni_macro_assembler_riscv64.cc | 75 if ((core_spill_mask & (1u << RA)) != 0u) { in BuildFrame()
77 __ Stored(RA, SP, offset); in BuildFrame()
78 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(RA), offset); in BuildFrame()
80 for (uint32_t reg : HighToLowBits(core_spill_mask & ~(1u << RA))) { in BuildFrame()
111 for (uint32_t reg : LowToHighBits(core_spill_mask & ~(1u << RA))) { in RemoveFrame()
116 if ((core_spill_mask & (1u << RA)) != 0u) { in RemoveFrame()
117 __ Loadd(RA, SP, offset); in RemoveFrame()
118 __ cfi().Restore(dwarf::Reg::Riscv64Core(RA)); in RemoveFrame()
448 __ Loadd(RA, base.AsXRegister(), offs.Int32Value()); in Call()
449 __ Jalr(RA); in Call()
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| D | managed_register_riscv64_test.cc | 37 reg = Riscv64ManagedRegister::FromXRegister(RA); in TEST()
41 EXPECT_EQ(RA, reg.AsXRegister()); in TEST()
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| D | assembler_riscv64.cc | 102 if (rd == RA && rs1 != Zero && offset == 0) { in Jalr()
6261 void Riscv64Assembler::Jal(int32_t offset) { Jal(RA, offset); } in Jal()
6265 void Riscv64Assembler::Jalr(XRegister rs) { Jalr(RA, rs, 0); } in Jalr()
6269 void Riscv64Assembler::Ret() { Jalr(Zero, RA, 0); } in Ret()
6517 Jal(RA, label, is_bare); in Jal()
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| D | assembler_riscv64_test.cc | 165 secondary_register_names_.emplace(RA, "ra"); in SetUpHelpers()
211 RA, in GetRegisters()
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 59 Riscv64ManagedRegister::FromXRegister(RA),
116 Riscv64ManagedRegister::FromXRegister(RA),
270 static_assert((kCoreCalleeSpillMask & (1 << RA)) != 0u); // Contains RA. in CalleeSaveRegisters()
273 Riscv64ManagedRegister::FromXRegister(RA))); in CalleeSaveRegisters()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 62 S0, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, RA
286 __ Loadd(RA, TR, entrypoint_offset); in EmitNativeCode()
289 __ Jalr(RA); in EmitNativeCode()
1326 Location temp = Location::RegisterLocation(RA); in GenerateGcRootFieldLoad()
1928 XRegister tmp = RA; // Use RA as temp. It is clobbered in the slow path anyway. in GenerateReferenceLoadWithBakerReadBarrier()
4178 __ Loadd(RA, temp, entry_point.Int32Value()); in VisitInvokeInterface()
4181 __ Jalr(RA); in VisitInvokeInterface()
5879 AddAllocatedRegister(Location::RegisterLocation(RA)); in CodeGeneratorRISCV64()
5914 XRegister tmp = RA; in MaybeIncrementHotness()
6093 __ Jr(RA); in GenerateFrameExit()
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| D | intrinsics_riscv64.cc | 1461 static constexpr Location kBakerReadBarrierTemp = Location::RegisterLocation(RA);
2721 static constexpr Location kBakerReadBarrierTemp = Location::RegisterLocation(RA); in GenUnsafeGetAndUpdate()
4479 static constexpr Location kBakerReadBarrierTemp = Location::RegisterLocation(RA); in GenerateVarHandleGetAndUpdate()
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| /art/disassembler/ |
| D | disassembler_riscv64.cc | 45 RA = 1, enumerator
391 if (rd != Zero && rd != RA) { in Print32Jal()
415 if (rd == Zero && rs1 == RA && imm12 == 0) { in Print32Jalr()
419 } else if (rd == RA && imm12 == 0) { in Print32Jalr()
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