Searched refs:S10 (Results 1 – 11 of 11) sorted by relevance
| /art/runtime/arch/arm/ |
| D | registers_arm.h | 70 S10 = 10, enumerator
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| D | context_arm.cc | 92 fprs_[S10] = nullptr; in SmashCallerSaves()
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| D | callee_save_frame_arm.h | 50 (1 << art::arm::S8) | (1 << art::arm::S9) | (1 << art::arm::S10) | (1 << art::arm::S11) |
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| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 58 S10 = 26, // X26, callee-saved 10 enumerator
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| D | callee_save_frame_riscv64.h | 40 (1 << art::riscv64::S10) | (1 << art::riscv64::S11);
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 166 S10 = 10, enumerator
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| /art/compiler/jni/quick/riscv64/ |
| D | calling_convention_riscv64.cc | 57 Riscv64ManagedRegister::FromXRegister(S10),
114 Riscv64ManagedRegister::FromXRegister(S10),
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 56 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 717 EXPECT_TRUE(vixl::aarch64::s10.Is(Arm64Assembler::reg_s(S10))); in TEST()
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64_test.cc | 190 secondary_register_names_.emplace(S10, "s10"); in SetUpHelpers()
236 S10, in GetRegisters()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.cc | 62 S0, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, RA
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