1 /* 2 * Copyright (C) 2019 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _EXYNOSDEVICEINTERFACE_H 18 #define _EXYNOSDEVICEINTERFACE_H 19 20 #include "ExynosDisplayInterface.h" 21 #include "ExynosHWCHelper.h" 22 #include "drmeventlistener.h" 23 24 struct hwc_dpp_size_range { 25 uint32_t min; 26 uint32_t max; 27 uint32_t align; 28 }; 29 30 struct hwc_dpp_restriction { 31 struct hwc_dpp_size_range src_f_w; 32 struct hwc_dpp_size_range src_f_h; 33 struct hwc_dpp_size_range src_w; 34 struct hwc_dpp_size_range src_h; 35 uint32_t src_x_align; 36 uint32_t src_y_align; 37 struct hwc_dpp_size_range dst_f_w; 38 struct hwc_dpp_size_range dst_f_h; 39 struct hwc_dpp_size_range dst_w; 40 struct hwc_dpp_size_range dst_h; 41 uint32_t dst_x_align; 42 uint32_t dst_y_align; 43 struct hwc_dpp_size_range blk_w; 44 struct hwc_dpp_size_range blk_h; 45 uint32_t blk_x_align; 46 uint32_t blk_y_align; 47 uint32_t src_h_rot_max; 48 std::vector<uint32_t> formats; 49 uint32_t scale_down; 50 uint32_t scale_up; 51 }; 52 53 struct hwc_dpp_ch_restriction { 54 int id; 55 unsigned long attr; 56 struct hwc_dpp_restriction restriction; 57 }; 58 59 struct hwc_dpp_restrictions_info { 60 uint32_t ver; 61 /* dpp_chs : Normal DPP DMA Channels for window composition */ 62 std::vector<hwc_dpp_ch_restriction> dpp_chs; 63 /* spp_chs : Special DPP DMA Channels for SPP (Speicial Purpose Plane) */ 64 std::vector<hwc_dpp_ch_restriction> spp_chs; 65 uint32_t ppc = 0; 66 uint32_t max_disp_freq = 0; 67 }; 68 69 /* for restriction query */ 70 typedef struct dpu_dpp_info { 71 struct hwc_dpp_restrictions_info dpuInfo; 72 bool overlap[16] = {false, }; 73 } dpu_dpp_info_t; 74 75 class ExynosDevice; 76 class ExynosDeviceInterface { 77 protected: 78 ExynosDevice *mExynosDevice = NULL; 79 bool mUseQuery = false; 80 // Gathered DPU resctrictions 81 dpu_dpp_info_t mDPUInfo; 82 public: ~ExynosDeviceInterface()83 virtual ~ExynosDeviceInterface(){}; 84 virtual void init(ExynosDevice *exynosDevice) = 0; 85 virtual void postInit() = 0; initDisplayInterface(std::unique_ptr<ExynosDisplayInterface> __unused & dispInterface)86 virtual int32_t initDisplayInterface( 87 std::unique_ptr<ExynosDisplayInterface> __unused &dispInterface) { 88 return 0; 89 }; 90 /* Fill mDPUInfo according to interface type */ 91 virtual void updateRestrictions() = 0; getUseQuery()92 virtual bool getUseQuery() { return mUseQuery; }; 93 registerSysfsEventHandler(std::shared_ptr<DrmSysfsEventHandler> __unused handler)94 virtual int32_t registerSysfsEventHandler( 95 std::shared_ptr<DrmSysfsEventHandler> __unused handler) { 96 return android::INVALID_OPERATION; 97 } unregisterSysfsEventHandler(int __unused sysfsFd)98 virtual int32_t unregisterSysfsEventHandler(int __unused sysfsFd) { 99 return android::INVALID_OPERATION; 100 } 101 getNumDPPChs()102 uint32_t getNumDPPChs() { return mDPUInfo.dpuInfo.dpp_chs.size(); }; getNumSPPChs()103 uint32_t getNumSPPChs() { return mDPUInfo.dpuInfo.spp_chs.size(); }; getSPPChId(uint32_t index)104 uint32_t getSPPChId(uint32_t index) { return mDPUInfo.dpuInfo.spp_chs.at(index).id; }; getSPPChAttr(uint32_t index)105 uint64_t getSPPChAttr(uint32_t index) { return mDPUInfo.dpuInfo.spp_chs.at(index).attr; }; 106 getExynosDevice()107 ExynosDevice* getExynosDevice() {return mExynosDevice;}; 108 protected: 109 /* Make dpu restrictions using mDPUInfo */ 110 int32_t makeDPURestrictions(); 111 /* Update feature table using mDPUInfo */ 112 int32_t updateFeatureTable(); 113 /* Print restriction */ 114 void printDppRestriction(struct hwc_dpp_ch_restriction res); 115 public: 116 uint32_t mType = INTERFACE_TYPE_NONE; 117 }; 118 #endif //_EXYNOSDEVICEINTERFACE_H 119