1 /*
2 * Copyright (C) 2017 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <stdint.h>
18
19 #include <memory>
20
21 #include <android-base/silent_death_test.h>
22 #include <gtest/gtest.h>
23
24 #include <unwindstack/Elf.h>
25 #include <unwindstack/ElfInterface.h>
26 #include <unwindstack/MachineRiscv64.h>
27 #include <unwindstack/MapInfo.h>
28 #include <unwindstack/RegsArm.h>
29 #include <unwindstack/RegsArm64.h>
30 #include <unwindstack/RegsRiscv64.h>
31 #include <unwindstack/RegsX86.h>
32 #include <unwindstack/RegsX86_64.h>
33
34 #include "ElfFake.h"
35 #include "RegsFake.h"
36 #include "utils/MemoryFake.h"
37
38 namespace unwindstack {
39
40 class RegsTest : public ::testing::Test {
41 protected:
SetUp()42 void SetUp() override {
43 fake_memory_ = new MemoryFake;
44 std::shared_ptr<Memory> memory(fake_memory_);
45 elf_.reset(new ElfFake(memory));
46 elf_interface_ = new ElfInterfaceFake(memory);
47 elf_->FakeSetInterface(elf_interface_);
48 }
49
50 ElfInterfaceFake* elf_interface_;
51 MemoryFake* fake_memory_;
52 std::unique_ptr<ElfFake> elf_;
53 };
54
TEST_F(RegsTest,regs32)55 TEST_F(RegsTest, regs32) {
56 RegsImplFake<uint32_t> regs32(50);
57 ASSERT_EQ(50U, regs32.total_regs());
58
59 uint32_t* raw = reinterpret_cast<uint32_t*>(regs32.RawData());
60 for (size_t i = 0; i < 50; i++) {
61 raw[i] = 0xf0000000 + i;
62 }
63 regs32.set_pc(0xf0120340);
64 regs32.set_sp(0xa0ab0cd0);
65
66 for (size_t i = 0; i < 50; i++) {
67 ASSERT_EQ(0xf0000000U + i, regs32[i]) << "Failed comparing register " << i;
68 }
69
70 ASSERT_EQ(0xf0120340U, regs32.pc());
71 ASSERT_EQ(0xa0ab0cd0U, regs32.sp());
72
73 regs32[32] = 10;
74 ASSERT_EQ(10U, regs32[32]);
75 }
76
TEST_F(RegsTest,regs64)77 TEST_F(RegsTest, regs64) {
78 RegsImplFake<uint64_t> regs64(30);
79 ASSERT_EQ(30U, regs64.total_regs());
80
81 uint64_t* raw = reinterpret_cast<uint64_t*>(regs64.RawData());
82 for (size_t i = 0; i < 30; i++) {
83 raw[i] = 0xf123456780000000UL + i;
84 }
85 regs64.set_pc(0xf123456780102030UL);
86 regs64.set_sp(0xa123456780a0b0c0UL);
87
88 for (size_t i = 0; i < 30; i++) {
89 ASSERT_EQ(0xf123456780000000U + i, regs64[i]) << "Failed reading register " << i;
90 }
91
92 ASSERT_EQ(0xf123456780102030UL, regs64.pc());
93 ASSERT_EQ(0xa123456780a0b0c0UL, regs64.sp());
94
95 regs64[8] = 10;
96 ASSERT_EQ(10U, regs64[8]);
97 }
98
TEST_F(RegsTest,rel_pc)99 TEST_F(RegsTest, rel_pc) {
100 EXPECT_EQ(4U, GetPcAdjustment(0x10, elf_.get(), ARCH_ARM64));
101 EXPECT_EQ(4U, GetPcAdjustment(0x4, elf_.get(), ARCH_ARM64));
102 EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_ARM64));
103 EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM64));
104 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM64));
105 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_ARM64));
106
107 EXPECT_EQ(4U, GetPcAdjustment(0x10, elf_.get(), ARCH_RISCV64));
108 EXPECT_EQ(4U, GetPcAdjustment(0x4, elf_.get(), ARCH_RISCV64));
109 EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_RISCV64));
110 EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_RISCV64));
111 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_RISCV64));
112 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_RISCV64));
113
114 EXPECT_EQ(1U, GetPcAdjustment(0x100, elf_.get(), ARCH_X86));
115 EXPECT_EQ(1U, GetPcAdjustment(0x2, elf_.get(), ARCH_X86));
116 EXPECT_EQ(1U, GetPcAdjustment(0x1, elf_.get(), ARCH_X86));
117 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_X86));
118
119 EXPECT_EQ(1U, GetPcAdjustment(0x100, elf_.get(), ARCH_X86_64));
120 EXPECT_EQ(1U, GetPcAdjustment(0x2, elf_.get(), ARCH_X86_64));
121 EXPECT_EQ(1U, GetPcAdjustment(0x1, elf_.get(), ARCH_X86_64));
122 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_X86_64));
123 }
124
TEST_F(RegsTest,rel_pc_arm)125 TEST_F(RegsTest, rel_pc_arm) {
126 // Check fence posts.
127 elf_->FakeSetLoadBias(0);
128 EXPECT_EQ(2U, GetPcAdjustment(0x5, elf_.get(), ARCH_ARM));
129 EXPECT_EQ(2U, GetPcAdjustment(0x4, elf_.get(), ARCH_ARM));
130 EXPECT_EQ(2U, GetPcAdjustment(0x3, elf_.get(), ARCH_ARM));
131 EXPECT_EQ(2U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM));
132 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM));
133 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_ARM));
134
135 elf_->FakeSetLoadBias(0x100);
136 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM));
137 EXPECT_EQ(2U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM));
138 EXPECT_EQ(2U, GetPcAdjustment(0xff, elf_.get(), ARCH_ARM));
139 EXPECT_EQ(2U, GetPcAdjustment(0x105, elf_.get(), ARCH_ARM));
140 EXPECT_EQ(2U, GetPcAdjustment(0x104, elf_.get(), ARCH_ARM));
141 EXPECT_EQ(2U, GetPcAdjustment(0x103, elf_.get(), ARCH_ARM));
142 EXPECT_EQ(2U, GetPcAdjustment(0x102, elf_.get(), ARCH_ARM));
143 EXPECT_EQ(0U, GetPcAdjustment(0x101, elf_.get(), ARCH_ARM));
144 EXPECT_EQ(0U, GetPcAdjustment(0x100, elf_.get(), ARCH_ARM));
145
146 // Check thumb instructions handling.
147 elf_->FakeSetLoadBias(0);
148 fake_memory_->SetData32(0x2000, 0);
149 EXPECT_EQ(2U, GetPcAdjustment(0x2005, elf_.get(), ARCH_ARM));
150 fake_memory_->SetData32(0x2000, 0xe000f000);
151 EXPECT_EQ(4U, GetPcAdjustment(0x2005, elf_.get(), ARCH_ARM));
152
153 elf_->FakeSetLoadBias(0x400);
154 fake_memory_->SetData32(0x2100, 0);
155 EXPECT_EQ(2U, GetPcAdjustment(0x2505, elf_.get(), ARCH_ARM));
156 fake_memory_->SetData32(0x2100, 0xf111f111);
157 EXPECT_EQ(4U, GetPcAdjustment(0x2505, elf_.get(), ARCH_ARM));
158 }
159
TEST_F(RegsTest,elf_invalid)160 TEST_F(RegsTest, elf_invalid) {
161 auto map_info = MapInfo::Create(0x1000, 0x2000, 0, 0, "");
162 std::shared_ptr<Memory> empty;
163 Elf* invalid_elf = new Elf(empty);
164 map_info->set_elf(invalid_elf);
165
166 EXPECT_EQ(0x500U, invalid_elf->GetRelPc(0x1500, map_info.get()));
167 EXPECT_EQ(2U, GetPcAdjustment(0x500U, invalid_elf, ARCH_ARM));
168 EXPECT_EQ(2U, GetPcAdjustment(0x511U, invalid_elf, ARCH_ARM));
169
170 EXPECT_EQ(0x600U, invalid_elf->GetRelPc(0x1600, map_info.get()));
171 EXPECT_EQ(4U, GetPcAdjustment(0x600U, invalid_elf, ARCH_ARM64));
172
173 EXPECT_EQ(0x600U, invalid_elf->GetRelPc(0x1600, map_info.get()));
174 EXPECT_EQ(4U, GetPcAdjustment(0x600U, invalid_elf, ARCH_RISCV64));
175
176 EXPECT_EQ(0x700U, invalid_elf->GetRelPc(0x1700, map_info.get()));
177 EXPECT_EQ(1U, GetPcAdjustment(0x700U, invalid_elf, ARCH_X86));
178
179 EXPECT_EQ(0x800U, invalid_elf->GetRelPc(0x1800, map_info.get()));
180 EXPECT_EQ(1U, GetPcAdjustment(0x800U, invalid_elf, ARCH_X86_64));
181 }
182
TEST_F(RegsTest,regs_convert)183 TEST_F(RegsTest, regs_convert) {
184 RegsArm arm;
185 EXPECT_EQ(0, arm.Convert(0));
186 EXPECT_EQ(0x1c22, arm.Convert(0x1c22));
187 RegsArm64 arm64;
188 EXPECT_EQ(0, arm64.Convert(0));
189 EXPECT_EQ(0x1c22, arm64.Convert(0x1c22));
190 RegsX86 x86;
191 EXPECT_EQ(0, x86.Convert(0));
192 EXPECT_EQ(0x1c22, x86.Convert(0x1c22));
193 RegsX86_64 x86_64;
194 EXPECT_EQ(0, x86_64.Convert(0));
195 EXPECT_EQ(0x1c22, x86_64.Convert(0x1c22));
196 }
197
TEST_F(RegsTest,arm_verify_sp_pc)198 TEST_F(RegsTest, arm_verify_sp_pc) {
199 RegsArm arm;
200 uint32_t* regs = reinterpret_cast<uint32_t*>(arm.RawData());
201 regs[13] = 0x100;
202 regs[15] = 0x200;
203 EXPECT_EQ(0x100U, arm.sp());
204 EXPECT_EQ(0x200U, arm.pc());
205 }
206
TEST_F(RegsTest,arm64_verify_sp_pc)207 TEST_F(RegsTest, arm64_verify_sp_pc) {
208 RegsArm64 arm64;
209 uint64_t* regs = reinterpret_cast<uint64_t*>(arm64.RawData());
210 regs[31] = 0xb100000000ULL;
211 regs[32] = 0xc200000000ULL;
212 EXPECT_EQ(0xb100000000U, arm64.sp());
213 EXPECT_EQ(0xc200000000U, arm64.pc());
214 }
215
TEST_F(RegsTest,riscv64_verify_sp_pc)216 TEST_F(RegsTest, riscv64_verify_sp_pc) {
217 RegsRiscv64 riscv64;
218 uint64_t* regs = reinterpret_cast<uint64_t*>(riscv64.RawData());
219 regs[2] = 0x212340000ULL;
220 regs[0] = 0x1abcd0000ULL;
221 EXPECT_EQ(0x212340000U, riscv64.sp());
222 EXPECT_EQ(0x1abcd0000U, riscv64.pc());
223 }
224
TEST_F(RegsTest,riscv_convert)225 TEST_F(RegsTest, riscv_convert) {
226 RegsRiscv64 regs;
227 EXPECT_EQ(0, regs.Convert(0));
228 EXPECT_EQ(RISCV64_REG_REAL_COUNT - 1, regs.Convert(RISCV64_REG_REAL_COUNT - 1));
229 EXPECT_EQ(RISCV64_REG_VLENB, regs.Convert(0x1c22));
230 EXPECT_EQ(RISCV64_REG_COUNT, regs.Convert(RISCV64_REG_VLENB));
231 }
232
233 #if defined(__riscv)
TEST_F(RegsTest,riscv_get_vlenb)234 TEST_F(RegsTest, riscv_get_vlenb) {
235 RegsRiscv64 regs;
236 EXPECT_NE(0U, regs.GetVlenbFromLocal());
237 EXPECT_NE(0U, regs.GetVlenbFromRemote(0));
238 }
239 #else
240 using RegsDeathTest = SilentDeathTest;
TEST_F(RegsDeathTest,riscv_get_vlenb)241 TEST_F(RegsDeathTest, riscv_get_vlenb) {
242 RegsRiscv64 regs;
243 ASSERT_DEATH(regs.GetVlenbFromLocal(), "");
244 ASSERT_DEATH(regs.GetVlenbFromRemote(0), "");
245 }
246 #endif
247
TEST_F(RegsTest,x86_verify_sp_pc)248 TEST_F(RegsTest, x86_verify_sp_pc) {
249 RegsX86 x86;
250 uint32_t* regs = reinterpret_cast<uint32_t*>(x86.RawData());
251 regs[4] = 0x23450000;
252 regs[8] = 0xabcd0000;
253 EXPECT_EQ(0x23450000U, x86.sp());
254 EXPECT_EQ(0xabcd0000U, x86.pc());
255 }
256
TEST_F(RegsTest,x86_64_verify_sp_pc)257 TEST_F(RegsTest, x86_64_verify_sp_pc) {
258 RegsX86_64 x86_64;
259 uint64_t* regs = reinterpret_cast<uint64_t*>(x86_64.RawData());
260 regs[7] = 0x1200000000ULL;
261 regs[16] = 0x4900000000ULL;
262 EXPECT_EQ(0x1200000000U, x86_64.sp());
263 EXPECT_EQ(0x4900000000U, x86_64.pc());
264 }
265
TEST_F(RegsTest,arm64_strip_pac_mask)266 TEST_F(RegsTest, arm64_strip_pac_mask) {
267 RegsArm64 arm64;
268 arm64.SetPseudoRegister(Arm64Reg::ARM64_PREG_RA_SIGN_STATE, 1);
269 arm64.SetPACMask(0x007fff8000000000ULL);
270 arm64.set_pc(0x0020007214bb3a04ULL);
271 EXPECT_EQ(0x0000007214bb3a04ULL, arm64.pc());
272 }
273
TEST_F(RegsTest,arm64_fallback_pc)274 TEST_F(RegsTest, arm64_fallback_pc) {
275 RegsArm64 arm64;
276 arm64.SetPACMask(0x007fff8000000000ULL);
277 arm64.set_pc(0x0020007214bb3a04ULL);
278 arm64.fallback_pc();
279 EXPECT_EQ(0x0000007214bb3a04ULL, arm64.pc());
280 }
281
TEST_F(RegsTest,machine_type)282 TEST_F(RegsTest, machine_type) {
283 RegsArm arm_regs;
284 EXPECT_EQ(ARCH_ARM, arm_regs.Arch());
285
286 RegsArm64 arm64_regs;
287 EXPECT_EQ(ARCH_ARM64, arm64_regs.Arch());
288
289 RegsRiscv64 riscv64_regs;
290 EXPECT_EQ(ARCH_RISCV64, riscv64_regs.Arch());
291
292 RegsX86 x86_regs;
293 EXPECT_EQ(ARCH_X86, x86_regs.Arch());
294
295 RegsX86_64 x86_64_regs;
296 EXPECT_EQ(ARCH_X86_64, x86_64_regs.Arch());
297 }
298
299 template <typename RegisterType>
clone_test(Regs * regs)300 void clone_test(Regs* regs) {
301 RegisterType* register_values = reinterpret_cast<RegisterType*>(regs->RawData());
302 int num_regs = regs->total_regs();
303 for (int i = 0; i < num_regs; ++i) {
304 register_values[i] = i;
305 }
306
307 std::unique_ptr<Regs> clone(regs->Clone());
308 ASSERT_EQ(regs->total_regs(), clone->total_regs());
309 RegisterType* clone_values = reinterpret_cast<RegisterType*>(clone->RawData());
310 for (int i = 0; i < num_regs; ++i) {
311 EXPECT_EQ(register_values[i], clone_values[i]);
312 EXPECT_NE(®ister_values[i], &clone_values[i]);
313 }
314 }
315
TEST_F(RegsTest,clone)316 TEST_F(RegsTest, clone) {
317 std::vector<std::unique_ptr<Regs>> regs;
318 regs.emplace_back(new RegsArm());
319 regs.emplace_back(new RegsArm64());
320 regs.emplace_back(new RegsRiscv64());
321 regs.emplace_back(new RegsX86());
322 regs.emplace_back(new RegsX86_64());
323
324 for (auto& r : regs) {
325 if (r->Is32Bit()) {
326 clone_test<uint32_t>(r.get());
327 } else {
328 clone_test<uint64_t>(r.get());
329 }
330 }
331 }
332
333 } // namespace unwindstack
334