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Searched defs:vs1 (Results 1 – 3 of 3) sorted by relevance

/art/test/123-compiler-regressions-mt/src/
DMain.java69 int[] vs1 = values; in thread2() local
99 int[] vs1; in thread2() local
/art/compiler/utils/riscv64/
Dassembler_riscv64.cc3792 void Riscv64Assembler::VAdd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAdd_vv()
3813 void Riscv64Assembler::VSub_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VSub_vv()
3843 void Riscv64Assembler::VMinu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMinu_vv()
3857 void Riscv64Assembler::VMin_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMin_vv()
3871 void Riscv64Assembler::VMaxu_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMaxu_vv()
3885 void Riscv64Assembler::VMax_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VMax_vv()
3899 void Riscv64Assembler::VAnd_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VAnd_vv()
3920 void Riscv64Assembler::VOr_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VOr_vv()
3940 void Riscv64Assembler::VXor_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VXor_vv()
3963 void Riscv64Assembler::VRgather_vv(VRegister vd, VRegister vs2, VRegister vs1, VM vm) { in VRgather_vv()
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Dassembler_riscv64_test.cc1941 return [](VRegister vd, Reg2, VRegister vs1, Riscv64Assembler::VM vm) { in VXVVmSkipV0VmAndNoR1R3Overlap()
1954 return [](VRegister vd, VRegister vs2, VRegister vs1, Riscv64Assembler::VM vm) { in VXVVmSkipV0VmAndNoR1R2R3Overlap()
1985 return [](VRegister vd, VRegister vs2, VRegister vs1) { return vd != vs1 && vd != vs2; }; in VVVNoR1R2R3Overlap()