1 /*
2  * Copyright (C) 2015 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
18 #define ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
19 
20 #include "base/macros.h"
21 #include "code_generator.h"
22 #include "instruction_simplifier_shared.h"
23 #include "locations.h"
24 #include "nodes.h"
25 #include "utils/arm64/assembler_arm64.h"
26 
27 // TODO(VIXL): Make VIXL compile with -Wshadow.
28 #pragma GCC diagnostic push
29 #pragma GCC diagnostic ignored "-Wshadow"
30 #include "aarch64/disasm-aarch64.h"
31 #include "aarch64/macro-assembler-aarch64.h"
32 #include "aarch64/simulator-aarch64.h"
33 #pragma GCC diagnostic pop
34 
35 namespace art HIDDEN {
36 
37 using helpers::CanFitInShifterOperand;
38 using helpers::HasShifterOperand;
39 
40 namespace arm64 {
41 namespace helpers {
42 
43 // Convenience helpers to ease conversion to and from VIXL operands.
44 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
45               "Unexpected values for register codes.");
46 
VIXLRegCodeFromART(int code)47 inline int VIXLRegCodeFromART(int code) {
48   if (code == SP) {
49     return vixl::aarch64::kSPRegInternalCode;
50   }
51   if (code == XZR) {
52     return vixl::aarch64::kZeroRegCode;
53   }
54   return code;
55 }
56 
ARTRegCodeFromVIXL(int code)57 inline int ARTRegCodeFromVIXL(int code) {
58   if (code == vixl::aarch64::kSPRegInternalCode) {
59     return SP;
60   }
61   if (code == vixl::aarch64::kZeroRegCode) {
62     return XZR;
63   }
64   return code;
65 }
66 
XRegisterFrom(Location location)67 inline vixl::aarch64::Register XRegisterFrom(Location location) {
68   DCHECK(location.IsRegister()) << location;
69   return vixl::aarch64::XRegister(VIXLRegCodeFromART(location.reg()));
70 }
71 
WRegisterFrom(Location location)72 inline vixl::aarch64::Register WRegisterFrom(Location location) {
73   DCHECK(location.IsRegister()) << location;
74   return vixl::aarch64::WRegister(VIXLRegCodeFromART(location.reg()));
75 }
76 
RegisterFrom(Location location,DataType::Type type)77 inline vixl::aarch64::Register RegisterFrom(Location location, DataType::Type type) {
78   DCHECK(type != DataType::Type::kVoid && !DataType::IsFloatingPointType(type)) << type;
79   return type == DataType::Type::kInt64 ? XRegisterFrom(location) : WRegisterFrom(location);
80 }
81 
OutputRegister(HInstruction * instr)82 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) {
83   return RegisterFrom(instr->GetLocations()->Out(), instr->GetType());
84 }
85 
InputRegisterAt(HInstruction * instr,int input_index)86 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) {
87   return RegisterFrom(instr->GetLocations()->InAt(input_index),
88                       instr->InputAt(input_index)->GetType());
89 }
90 
DRegisterFrom(Location location)91 inline vixl::aarch64::VRegister DRegisterFrom(Location location) {
92   DCHECK(location.IsFpuRegister()) << location;
93   return vixl::aarch64::DRegister(location.reg());
94 }
95 
QRegisterFrom(Location location)96 inline vixl::aarch64::VRegister QRegisterFrom(Location location) {
97   DCHECK(location.IsFpuRegister()) << location;
98   return vixl::aarch64::QRegister(location.reg());
99 }
100 
VRegisterFrom(Location location)101 inline vixl::aarch64::VRegister VRegisterFrom(Location location) {
102   DCHECK(location.IsFpuRegister()) << location;
103   return vixl::aarch64::VRegister(location.reg());
104 }
105 
ZRegisterFrom(Location location)106 inline vixl::aarch64::ZRegister ZRegisterFrom(Location location) {
107   DCHECK(location.IsFpuRegister()) << location;
108   return vixl::aarch64::ZRegister(location.reg());
109 }
110 
SRegisterFrom(Location location)111 inline vixl::aarch64::VRegister SRegisterFrom(Location location) {
112   DCHECK(location.IsFpuRegister()) << location;
113   return vixl::aarch64::SRegister(location.reg());
114 }
115 
HRegisterFrom(Location location)116 inline vixl::aarch64::VRegister HRegisterFrom(Location location) {
117   DCHECK(location.IsFpuRegister()) << location;
118   return vixl::aarch64::HRegister(location.reg());
119 }
120 
FPRegisterFrom(Location location,DataType::Type type)121 inline vixl::aarch64::VRegister FPRegisterFrom(Location location, DataType::Type type) {
122   DCHECK(DataType::IsFloatingPointType(type)) << type;
123   return type == DataType::Type::kFloat64 ? DRegisterFrom(location) : SRegisterFrom(location);
124 }
125 
OutputFPRegister(HInstruction * instr)126 inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) {
127   return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType());
128 }
129 
InputFPRegisterAt(HInstruction * instr,int input_index)130 inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) {
131   return FPRegisterFrom(instr->GetLocations()->InAt(input_index),
132                         instr->InputAt(input_index)->GetType());
133 }
134 
CPURegisterFrom(Location location,DataType::Type type)135 inline vixl::aarch64::CPURegister CPURegisterFrom(Location location, DataType::Type type) {
136   return DataType::IsFloatingPointType(type)
137       ? vixl::aarch64::CPURegister(FPRegisterFrom(location, type))
138       : vixl::aarch64::CPURegister(RegisterFrom(location, type));
139 }
140 
OutputCPURegister(HInstruction * instr)141 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) {
142   return DataType::IsFloatingPointType(instr->GetType())
143       ? static_cast<vixl::aarch64::CPURegister>(OutputFPRegister(instr))
144       : static_cast<vixl::aarch64::CPURegister>(OutputRegister(instr));
145 }
146 
InputCPURegisterAt(HInstruction * instr,int index)147 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) {
148   return DataType::IsFloatingPointType(instr->InputAt(index)->GetType())
149       ? static_cast<vixl::aarch64::CPURegister>(InputFPRegisterAt(instr, index))
150       : static_cast<vixl::aarch64::CPURegister>(InputRegisterAt(instr, index));
151 }
152 
InputCPURegisterOrZeroRegAt(HInstruction * instr,int index)153 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr,
154                                                                      int index) {
155   HInstruction* input = instr->InputAt(index);
156   DataType::Type input_type = input->GetType();
157   if (IsZeroBitPattern(input)) {
158     return (DataType::Size(input_type) >= vixl::aarch64::kXRegSizeInBytes)
159         ? vixl::aarch64::Register(vixl::aarch64::xzr)
160         : vixl::aarch64::Register(vixl::aarch64::wzr);
161   }
162   return InputCPURegisterAt(instr, index);
163 }
164 
Int64FromLocation(Location location)165 inline int64_t Int64FromLocation(Location location) {
166   return Int64FromConstant(location.GetConstant());
167 }
168 
OperandFrom(Location location,DataType::Type type)169 inline vixl::aarch64::Operand OperandFrom(Location location, DataType::Type type) {
170   if (location.IsRegister()) {
171     return vixl::aarch64::Operand(RegisterFrom(location, type));
172   } else {
173     return vixl::aarch64::Operand(Int64FromLocation(location));
174   }
175 }
176 
InputOperandAt(HInstruction * instr,int input_index)177 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) {
178   return OperandFrom(instr->GetLocations()->InAt(input_index),
179                      instr->InputAt(input_index)->GetType());
180 }
181 
StackOperandFrom(Location location)182 inline vixl::aarch64::MemOperand StackOperandFrom(Location location) {
183   return vixl::aarch64::MemOperand(vixl::aarch64::sp, location.GetStackIndex());
184 }
185 
SveStackOperandFrom(Location location)186 inline vixl::aarch64::SVEMemOperand SveStackOperandFrom(Location location) {
187   return vixl::aarch64::SVEMemOperand(vixl::aarch64::sp, location.GetStackIndex());
188 }
189 
190 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
191                                                     size_t offset = 0) {
192   // A heap reference must be 32bit, so fit in a W register.
193   DCHECK(base.IsW());
194   return vixl::aarch64::MemOperand(base.X(), offset);
195 }
196 
197 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
198                                                     const vixl::aarch64::Register& regoffset,
199                                                     vixl::aarch64::Shift shift = vixl::aarch64::LSL,
200                                                     unsigned shift_amount = 0) {
201   // A heap reference must be 32bit, so fit in a W register.
202   DCHECK(base.IsW());
203   return vixl::aarch64::MemOperand(base.X(), regoffset, shift, shift_amount);
204 }
205 
HeapOperand(const vixl::aarch64::Register & base,Offset offset)206 inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base,
207                                                     Offset offset) {
208   return HeapOperand(base, offset.SizeValue());
209 }
210 
HeapOperandFrom(Location location,Offset offset)211 inline vixl::aarch64::MemOperand HeapOperandFrom(Location location, Offset offset) {
212   return HeapOperand(RegisterFrom(location, DataType::Type::kReference), offset);
213 }
214 
LocationFrom(const vixl::aarch64::Register & reg)215 inline Location LocationFrom(const vixl::aarch64::Register& reg) {
216   return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.GetCode()));
217 }
218 
LocationFrom(const vixl::aarch64::VRegister & fpreg)219 inline Location LocationFrom(const vixl::aarch64::VRegister& fpreg) {
220   return Location::FpuRegisterLocation(fpreg.GetCode());
221 }
222 
LocationFrom(const vixl::aarch64::ZRegister & zreg)223 inline Location LocationFrom(const vixl::aarch64::ZRegister& zreg) {
224   return Location::FpuRegisterLocation(zreg.GetCode());
225 }
226 
OperandFromMemOperand(const vixl::aarch64::MemOperand & mem_op)227 inline vixl::aarch64::Operand OperandFromMemOperand(
228     const vixl::aarch64::MemOperand& mem_op) {
229   if (mem_op.IsImmediateOffset()) {
230     return vixl::aarch64::Operand(mem_op.GetOffset());
231   } else {
232     DCHECK(mem_op.IsRegisterOffset());
233     if (mem_op.GetExtend() != vixl::aarch64::NO_EXTEND) {
234       return vixl::aarch64::Operand(mem_op.GetRegisterOffset(),
235                                     mem_op.GetExtend(),
236                                     mem_op.GetShiftAmount());
237     } else if (mem_op.GetShift() != vixl::aarch64::NO_SHIFT) {
238       return vixl::aarch64::Operand(mem_op.GetRegisterOffset(),
239                                     mem_op.GetShift(),
240                                     mem_op.GetShiftAmount());
241     } else {
242       LOG(FATAL) << "Should not reach here";
243       UNREACHABLE();
244     }
245   }
246 }
247 
AddSubCanEncodeAsImmediate(int64_t value)248 inline bool AddSubCanEncodeAsImmediate(int64_t value) {
249   // If `value` does not fit but `-value` does, VIXL will automatically use
250   // the 'opposite' instruction.
251   return vixl::aarch64::Assembler::IsImmAddSub(value)
252       || vixl::aarch64::Assembler::IsImmAddSub(-value);
253 }
254 
Arm64CanEncodeConstantAsImmediate(HConstant * constant,HInstruction * instr)255 inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) {
256   int64_t value = CodeGenerator::GetInt64ValueOf(constant);
257 
258   // TODO: Improve this when IsSIMDConstantEncodable method is implemented in VIXL.
259   if (instr->IsVecReplicateScalar()) {
260     if (constant->IsLongConstant()) {
261       return false;
262     } else if (constant->IsFloatConstant()) {
263       return vixl::aarch64::Assembler::IsImmFP32(constant->AsFloatConstant()->GetValue());
264     } else if (constant->IsDoubleConstant()) {
265       return vixl::aarch64::Assembler::IsImmFP64(constant->AsDoubleConstant()->GetValue());
266     }
267     return IsUint<8>(value);
268   }
269 
270   // Code generation for Min/Max:
271   //    Cmp left_op, right_op
272   //    Csel dst, left_op, right_op, cond
273   if (instr->IsMin() || instr->IsMax()) {
274     if (constant->GetUses().HasExactlyOneElement()) {
275       // If value can be encoded as immediate for the Cmp, then let VIXL handle
276       // the constant generation for the Csel.
277       return AddSubCanEncodeAsImmediate(value);
278     }
279     // These values are encodable as immediates for Cmp and VIXL will use csinc and csinv
280     // with the zr register as right_op, hence no constant generation is required.
281     return constant->IsZeroBitPattern() || constant->IsOne() || constant->IsMinusOne();
282   }
283 
284   // For single uses we let VIXL handle the constant generation since it will
285   // use registers that are not managed by the register allocator (wip0, wip1).
286   if (constant->GetUses().HasExactlyOneElement()) {
287     return true;
288   }
289 
290   // Our code generator ensures shift distances are within an encodable range.
291   if (instr->IsRor()) {
292     return true;
293   }
294 
295   if (instr->IsAnd() || instr->IsOr() || instr->IsXor()) {
296     // Uses logical operations.
297     return vixl::aarch64::Assembler::IsImmLogical(value, vixl::aarch64::kXRegSize);
298   } else if (instr->IsNeg()) {
299     // Uses mov -immediate.
300     return vixl::aarch64::Assembler::IsImmMovn(value, vixl::aarch64::kXRegSize);
301   } else {
302     DCHECK(instr->IsAdd() ||
303            instr->IsIntermediateAddress() ||
304            instr->IsBoundsCheck() ||
305            instr->IsCompare() ||
306            instr->IsCondition() ||
307            instr->IsSub())
308         << instr->DebugName();
309     // Uses aliases of ADD/SUB instructions.
310     return AddSubCanEncodeAsImmediate(value);
311   }
312 }
313 
ARM64EncodableConstantOrRegister(HInstruction * constant,HInstruction * instr)314 inline Location ARM64EncodableConstantOrRegister(HInstruction* constant, HInstruction* instr) {
315   if (constant->IsConstant() && Arm64CanEncodeConstantAsImmediate(constant->AsConstant(), instr)) {
316     return Location::ConstantLocation(constant);
317   }
318 
319   return Location::RequiresRegister();
320 }
321 
322 // Check if registers in art register set have the same register code in vixl. If the register
323 // codes are same, we can initialize vixl register list simply by the register masks. Currently,
324 // only SP/WSP and ZXR/WZR codes are different between art and vixl.
325 // Note: This function is only used for debug checks.
ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers,size_t num_core,uint32_t art_fpu_registers,size_t num_fpu)326 inline bool ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers,
327                                             size_t num_core,
328                                             uint32_t art_fpu_registers,
329                                             size_t num_fpu) {
330   // The register masks won't work if the number of register is larger than 32.
331   DCHECK_GE(sizeof(art_core_registers) * 8, num_core);
332   DCHECK_GE(sizeof(art_fpu_registers) * 8, num_fpu);
333   for (size_t art_reg_code = 0;  art_reg_code < num_core; ++art_reg_code) {
334     if (RegisterSet::Contains(art_core_registers, art_reg_code)) {
335       if (art_reg_code != static_cast<size_t>(VIXLRegCodeFromART(art_reg_code))) {
336         return false;
337       }
338     }
339   }
340   // There is no register code translation for float registers.
341   return true;
342 }
343 
ShiftFromOpKind(HDataProcWithShifterOp::OpKind op_kind)344 inline vixl::aarch64::Shift ShiftFromOpKind(HDataProcWithShifterOp::OpKind op_kind) {
345   switch (op_kind) {
346     case HDataProcWithShifterOp::kASR: return vixl::aarch64::ASR;
347     case HDataProcWithShifterOp::kLSL: return vixl::aarch64::LSL;
348     case HDataProcWithShifterOp::kLSR: return vixl::aarch64::LSR;
349     default:
350       LOG(FATAL) << "Unexpected op kind " << op_kind;
351       UNREACHABLE();
352   }
353 }
354 
ExtendFromOpKind(HDataProcWithShifterOp::OpKind op_kind)355 inline vixl::aarch64::Extend ExtendFromOpKind(HDataProcWithShifterOp::OpKind op_kind) {
356   switch (op_kind) {
357     case HDataProcWithShifterOp::kUXTB: return vixl::aarch64::UXTB;
358     case HDataProcWithShifterOp::kUXTH: return vixl::aarch64::UXTH;
359     case HDataProcWithShifterOp::kUXTW: return vixl::aarch64::UXTW;
360     case HDataProcWithShifterOp::kSXTB: return vixl::aarch64::SXTB;
361     case HDataProcWithShifterOp::kSXTH: return vixl::aarch64::SXTH;
362     case HDataProcWithShifterOp::kSXTW: return vixl::aarch64::SXTW;
363     default:
364       LOG(FATAL) << "Unexpected op kind " << op_kind;
365       UNREACHABLE();
366   }
367 }
368 
ShifterOperandSupportsExtension(HInstruction * instruction)369 inline bool ShifterOperandSupportsExtension(HInstruction* instruction) {
370   DCHECK(HasShifterOperand(instruction, InstructionSet::kArm64));
371   // Although the `neg` instruction is an alias of the `sub` instruction, `HNeg`
372   // does *not* support extension. This is because the `extended register` form
373   // of the `sub` instruction interprets the left register with code 31 as the
374   // stack pointer and not the zero register. (So does the `immediate` form.) In
375   // the other form `shifted register, the register with code 31 is interpreted
376   // as the zero register.
377   return instruction->IsAdd() || instruction->IsSub();
378 }
379 
380 }  // namespace helpers
381 }  // namespace arm64
382 }  // namespace art
383 
384 #endif  // ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_
385