1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __UAPI_IVPU_DRM_H__ 8 #define __UAPI_IVPU_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_IVPU_DRIVER_MAJOR 1 14 #define DRM_IVPU_DRIVER_MINOR 0 15 #define DRM_IVPU_GET_PARAM 0x00 16 #define DRM_IVPU_SET_PARAM 0x01 17 #define DRM_IVPU_BO_CREATE 0x02 18 #define DRM_IVPU_BO_INFO 0x03 19 #define DRM_IVPU_SUBMIT 0x05 20 #define DRM_IVPU_BO_WAIT 0x06 21 #define DRM_IOCTL_IVPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param) 22 #define DRM_IOCTL_IVPU_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param) 23 #define DRM_IOCTL_IVPU_BO_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create) 24 #define DRM_IOCTL_IVPU_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info) 25 #define DRM_IOCTL_IVPU_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit) 26 #define DRM_IOCTL_IVPU_BO_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait) 27 #define DRM_IVPU_PARAM_DEVICE_ID 0 28 #define DRM_IVPU_PARAM_DEVICE_REVISION 1 29 #define DRM_IVPU_PARAM_PLATFORM_TYPE 2 30 #define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3 31 #define DRM_IVPU_PARAM_NUM_CONTEXTS 4 32 #define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5 33 #define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6 34 #define DRM_IVPU_PARAM_CONTEXT_ID 7 35 #define DRM_IVPU_PARAM_FW_API_VERSION 8 36 #define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9 37 #define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10 38 #define DRM_IVPU_PARAM_TILE_CONFIG 11 39 #define DRM_IVPU_PARAM_SKU 12 40 #define DRM_IVPU_PARAM_CAPABILITIES 13 41 #define DRM_IVPU_PLATFORM_TYPE_SILICON 0 42 #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0 43 #define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1 44 #define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2 45 #define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3 46 #define DRM_IVPU_JOB_PRIORITY_DEFAULT 0 47 #define DRM_IVPU_JOB_PRIORITY_IDLE 1 48 #define DRM_IVPU_JOB_PRIORITY_NORMAL 2 49 #define DRM_IVPU_JOB_PRIORITY_FOCUS 3 50 #define DRM_IVPU_JOB_PRIORITY_REALTIME 4 51 #define DRM_IVPU_CAP_METRIC_STREAMER 1 52 #define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2 53 struct drm_ivpu_param { 54 __u32 param; 55 __u32 index; 56 __u64 value; 57 }; 58 #define DRM_IVPU_BO_SHAVE_MEM 0x00000001 59 #define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM 60 #define DRM_IVPU_BO_MAPPABLE 0x00000002 61 #define DRM_IVPU_BO_DMA_MEM 0x00000004 62 #define DRM_IVPU_BO_CACHED 0x00000000 63 #define DRM_IVPU_BO_UNCACHED 0x00010000 64 #define DRM_IVPU_BO_WC 0x00020000 65 #define DRM_IVPU_BO_CACHE_MASK 0x00030000 66 #define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_DMA_MEM | DRM_IVPU_BO_CACHE_MASK) 67 struct drm_ivpu_bo_create { 68 __u64 size; 69 __u32 flags; 70 __u32 handle; 71 __u64 vpu_addr; 72 }; 73 struct drm_ivpu_bo_info { 74 __u32 handle; 75 __u32 flags; 76 __u64 vpu_addr; 77 __u64 mmap_offset; 78 __u64 size; 79 }; 80 #define DRM_IVPU_ENGINE_COMPUTE 0 81 #define DRM_IVPU_ENGINE_COPY 1 82 struct drm_ivpu_submit { 83 __u64 buffers_ptr; 84 __u32 buffer_count; 85 __u32 engine; 86 __u32 flags; 87 __u32 commands_offset; 88 __u32 priority; 89 }; 90 #define DRM_IVPU_JOB_STATUS_SUCCESS 0 91 #define DRM_IVPU_JOB_STATUS_ABORTED 256 92 struct drm_ivpu_bo_wait { 93 __u32 handle; 94 __u32 flags; 95 __s64 timeout_ns; 96 __u32 job_status; 97 __u32 pad; 98 }; 99 #ifdef __cplusplus 100 } 101 #endif 102 #endif 103