1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _COMEDI_H 8 #define _COMEDI_H 9 #define COMEDI_MAJORVERSION 0 10 #define COMEDI_MINORVERSION 7 11 #define COMEDI_MICROVERSION 76 12 #define VERSION "0.7.76" 13 #define COMEDI_MAJOR 98 14 #define COMEDI_NDEVICES 16 15 #define COMEDI_NDEVCONFOPTS 32 16 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 17 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 18 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 19 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 20 #define COMEDI_DEVCONF_AUX_DATA_HI 29 21 #define COMEDI_DEVCONF_AUX_DATA_LO 30 22 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 23 #define COMEDI_NAMELEN 20 24 #define CR_PACK(chan,rng,aref) ((((aref) & 0x3) << 24) | (((rng) & 0xff) << 16) | (chan)) 25 #define CR_PACK_FLAGS(chan,range,aref,flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) 26 #define CR_CHAN(a) ((a) & 0xffff) 27 #define CR_RANGE(a) (((a) >> 16) & 0xff) 28 #define CR_AREF(a) (((a) >> 24) & 0x03) 29 #define CR_FLAGS_MASK 0xfc000000 30 #define CR_ALT_FILTER 0x04000000 31 #define CR_DITHER CR_ALT_FILTER 32 #define CR_DEGLITCH CR_ALT_FILTER 33 #define CR_ALT_SOURCE 0x08000000 34 #define CR_EDGE 0x40000000 35 #define CR_INVERT 0x80000000 36 #define AREF_GROUND 0x00 37 #define AREF_COMMON 0x01 38 #define AREF_DIFF 0x02 39 #define AREF_OTHER 0x03 40 #define GPCT_RESET 0x0001 41 #define GPCT_SET_SOURCE 0x0002 42 #define GPCT_SET_GATE 0x0004 43 #define GPCT_SET_DIRECTION 0x0008 44 #define GPCT_SET_OPERATION 0x0010 45 #define GPCT_ARM 0x0020 46 #define GPCT_DISARM 0x0040 47 #define GPCT_GET_INT_CLK_FRQ 0x0080 48 #define GPCT_INT_CLOCK 0x0001 49 #define GPCT_EXT_PIN 0x0002 50 #define GPCT_NO_GATE 0x0004 51 #define GPCT_UP 0x0008 52 #define GPCT_DOWN 0x0010 53 #define GPCT_HWUD 0x0020 54 #define GPCT_SIMPLE_EVENT 0x0040 55 #define GPCT_SINGLE_PERIOD 0x0080 56 #define GPCT_SINGLE_PW 0x0100 57 #define GPCT_CONT_PULSE_OUT 0x0200 58 #define GPCT_SINGLE_PULSE_OUT 0x0400 59 #define INSN_MASK_WRITE 0x8000000 60 #define INSN_MASK_READ 0x4000000 61 #define INSN_MASK_SPECIAL 0x2000000 62 #define INSN_READ (0 | INSN_MASK_READ) 63 #define INSN_WRITE (1 | INSN_MASK_WRITE) 64 #define INSN_BITS (2 | INSN_MASK_READ | INSN_MASK_WRITE) 65 #define INSN_CONFIG (3 | INSN_MASK_READ | INSN_MASK_WRITE) 66 #define INSN_DEVICE_CONFIG (INSN_CONFIG | INSN_MASK_SPECIAL) 67 #define INSN_GTOD (4 | INSN_MASK_READ | INSN_MASK_SPECIAL) 68 #define INSN_WAIT (5 | INSN_MASK_WRITE | INSN_MASK_SPECIAL) 69 #define INSN_INTTRIG (6 | INSN_MASK_WRITE | INSN_MASK_SPECIAL) 70 #define CMDF_BOGUS 0x00000001 71 #define CMDF_PRIORITY 0x00000008 72 #define CMDF_WAKE_EOS 0x00000020 73 #define CMDF_WRITE 0x00000040 74 #define CMDF_RAWDATA 0x00000080 75 #define CMDF_ROUND_MASK 0x00030000 76 #define CMDF_ROUND_NEAREST 0x00000000 77 #define CMDF_ROUND_DOWN 0x00010000 78 #define CMDF_ROUND_UP 0x00020000 79 #define CMDF_ROUND_UP_NEXT 0x00030000 80 #define COMEDI_EV_START 0x00040000 81 #define COMEDI_EV_SCAN_BEGIN 0x00080000 82 #define COMEDI_EV_CONVERT 0x00100000 83 #define COMEDI_EV_SCAN_END 0x00200000 84 #define COMEDI_EV_STOP 0x00400000 85 #define TRIG_BOGUS CMDF_BOGUS 86 #define TRIG_RT CMDF_PRIORITY 87 #define TRIG_WAKE_EOS CMDF_WAKE_EOS 88 #define TRIG_WRITE CMDF_WRITE 89 #define TRIG_ROUND_MASK CMDF_ROUND_MASK 90 #define TRIG_ROUND_NEAREST CMDF_ROUND_NEAREST 91 #define TRIG_ROUND_DOWN CMDF_ROUND_DOWN 92 #define TRIG_ROUND_UP CMDF_ROUND_UP 93 #define TRIG_ROUND_UP_NEXT CMDF_ROUND_UP_NEXT 94 #define TRIG_ANY 0xffffffff 95 #define TRIG_INVALID 0x00000000 96 #define TRIG_NONE 0x00000001 97 #define TRIG_NOW 0x00000002 98 #define TRIG_FOLLOW 0x00000004 99 #define TRIG_TIME 0x00000008 100 #define TRIG_TIMER 0x00000010 101 #define TRIG_COUNT 0x00000020 102 #define TRIG_EXT 0x00000040 103 #define TRIG_INT 0x00000080 104 #define TRIG_OTHER 0x00000100 105 #define SDF_BUSY 0x0001 106 #define SDF_BUSY_OWNER 0x0002 107 #define SDF_LOCKED 0x0004 108 #define SDF_LOCK_OWNER 0x0008 109 #define SDF_MAXDATA 0x0010 110 #define SDF_FLAGS 0x0020 111 #define SDF_RANGETYPE 0x0040 112 #define SDF_PWM_COUNTER 0x0080 113 #define SDF_PWM_HBRIDGE 0x0100 114 #define SDF_CMD 0x1000 115 #define SDF_SOFT_CALIBRATED 0x2000 116 #define SDF_CMD_WRITE 0x4000 117 #define SDF_CMD_READ 0x8000 118 #define SDF_READABLE 0x00010000 119 #define SDF_WRITABLE 0x00020000 120 #define SDF_WRITEABLE SDF_WRITABLE 121 #define SDF_INTERNAL 0x00040000 122 #define SDF_GROUND 0x00100000 123 #define SDF_COMMON 0x00200000 124 #define SDF_DIFF 0x00400000 125 #define SDF_OTHER 0x00800000 126 #define SDF_DITHER 0x01000000 127 #define SDF_DEGLITCH 0x02000000 128 #define SDF_MMAP 0x04000000 129 #define SDF_RUNNING 0x08000000 130 #define SDF_LSAMPL 0x10000000 131 #define SDF_PACKED 0x20000000 132 enum comedi_subdevice_type { 133 COMEDI_SUBD_UNUSED, 134 COMEDI_SUBD_AI, 135 COMEDI_SUBD_AO, 136 COMEDI_SUBD_DI, 137 COMEDI_SUBD_DO, 138 COMEDI_SUBD_DIO, 139 COMEDI_SUBD_COUNTER, 140 COMEDI_SUBD_TIMER, 141 COMEDI_SUBD_MEMORY, 142 COMEDI_SUBD_CALIB, 143 COMEDI_SUBD_PROC, 144 COMEDI_SUBD_SERIAL, 145 COMEDI_SUBD_PWM 146 }; 147 enum comedi_io_direction { 148 COMEDI_INPUT = 0, 149 COMEDI_OUTPUT = 1, 150 COMEDI_OPENDRAIN = 2 151 }; 152 enum configuration_ids { 153 INSN_CONFIG_DIO_INPUT = COMEDI_INPUT, 154 INSN_CONFIG_DIO_OUTPUT = COMEDI_OUTPUT, 155 INSN_CONFIG_DIO_OPENDRAIN = COMEDI_OPENDRAIN, 156 INSN_CONFIG_ANALOG_TRIG = 16, 157 INSN_CONFIG_ALT_SOURCE = 20, 158 INSN_CONFIG_DIGITAL_TRIG = 21, 159 INSN_CONFIG_BLOCK_SIZE = 22, 160 INSN_CONFIG_TIMER_1 = 23, 161 INSN_CONFIG_FILTER = 24, 162 INSN_CONFIG_CHANGE_NOTIFY = 25, 163 INSN_CONFIG_SERIAL_CLOCK = 26, 164 INSN_CONFIG_BIDIRECTIONAL_DATA = 27, 165 INSN_CONFIG_DIO_QUERY = 28, 166 INSN_CONFIG_PWM_OUTPUT = 29, 167 INSN_CONFIG_GET_PWM_OUTPUT = 30, 168 INSN_CONFIG_ARM = 31, 169 INSN_CONFIG_DISARM = 32, 170 INSN_CONFIG_GET_COUNTER_STATUS = 33, 171 INSN_CONFIG_RESET = 34, 172 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, 173 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, 174 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, 175 INSN_CONFIG_SET_GATE_SRC = 2001, 176 INSN_CONFIG_GET_GATE_SRC = 2002, 177 INSN_CONFIG_SET_CLOCK_SRC = 2003, 178 INSN_CONFIG_GET_CLOCK_SRC = 2004, 179 INSN_CONFIG_SET_OTHER_SRC = 2005, 180 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, 181 INSN_CONFIG_SET_COUNTER_MODE = 4097, 182 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, 183 INSN_CONFIG_8254_READ_STATUS = 4098, 184 INSN_CONFIG_SET_ROUTING = 4099, 185 INSN_CONFIG_GET_ROUTING = 4109, 186 INSN_CONFIG_PWM_SET_PERIOD = 5000, 187 INSN_CONFIG_PWM_GET_PERIOD = 5001, 188 INSN_CONFIG_GET_PWM_STATUS = 5002, 189 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, 190 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004, 191 INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS = 5005, 192 }; 193 enum device_config_route_ids { 194 INSN_DEVICE_CONFIG_TEST_ROUTE = 0, 195 INSN_DEVICE_CONFIG_CONNECT_ROUTE = 1, 196 INSN_DEVICE_CONFIG_DISCONNECT_ROUTE = 2, 197 INSN_DEVICE_CONFIG_GET_ROUTES = 3, 198 }; 199 enum comedi_digital_trig_op { 200 COMEDI_DIGITAL_TRIG_DISABLE = 0, 201 COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1, 202 COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2 203 }; 204 enum comedi_support_level { 205 COMEDI_UNKNOWN_SUPPORT = 0, 206 COMEDI_SUPPORTED, 207 COMEDI_UNSUPPORTED 208 }; 209 enum comedi_counter_status_flags { 210 COMEDI_COUNTER_ARMED = 0x1, 211 COMEDI_COUNTER_COUNTING = 0x2, 212 COMEDI_COUNTER_TERMINAL_COUNT = 0x4, 213 }; 214 #define CIO 'd' 215 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig) 216 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo) 217 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo) 218 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo) 219 #define COMEDI_LOCK _IO(CIO, 5) 220 #define COMEDI_UNLOCK _IO(CIO, 6) 221 #define COMEDI_CANCEL _IO(CIO, 7) 222 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo) 223 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd) 224 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd) 225 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist) 226 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn) 227 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig) 228 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo) 229 #define COMEDI_POLL _IO(CIO, 15) 230 #define COMEDI_SETRSUBD _IO(CIO, 16) 231 #define COMEDI_SETWSUBD _IO(CIO, 17) 232 struct comedi_insn { 233 unsigned int insn; 234 unsigned int n; 235 unsigned int * data; 236 unsigned int subdev; 237 unsigned int chanspec; 238 unsigned int unused[3]; 239 }; 240 struct comedi_insnlist { 241 unsigned int n_insns; 242 struct comedi_insn * insns; 243 }; 244 struct comedi_cmd { 245 unsigned int subdev; 246 unsigned int flags; 247 unsigned int start_src; 248 unsigned int start_arg; 249 unsigned int scan_begin_src; 250 unsigned int scan_begin_arg; 251 unsigned int convert_src; 252 unsigned int convert_arg; 253 unsigned int scan_end_src; 254 unsigned int scan_end_arg; 255 unsigned int stop_src; 256 unsigned int stop_arg; 257 unsigned int * chanlist; 258 unsigned int chanlist_len; 259 short * data; 260 unsigned int data_len; 261 }; 262 struct comedi_chaninfo { 263 unsigned int subdev; 264 unsigned int * maxdata_list; 265 unsigned int * flaglist; 266 unsigned int * rangelist; 267 unsigned int unused[4]; 268 }; 269 struct comedi_rangeinfo { 270 unsigned int range_type; 271 void * range_ptr; 272 }; 273 struct comedi_krange { 274 int min; 275 int max; 276 unsigned int flags; 277 }; 278 struct comedi_subdinfo { 279 unsigned int type; 280 unsigned int n_chan; 281 unsigned int subd_flags; 282 unsigned int timer_type; 283 unsigned int len_chanlist; 284 unsigned int maxdata; 285 unsigned int flags; 286 unsigned int range_type; 287 unsigned int settling_time_0; 288 unsigned int insn_bits_support; 289 unsigned int unused[8]; 290 }; 291 struct comedi_devinfo { 292 unsigned int version_code; 293 unsigned int n_subdevs; 294 char driver_name[COMEDI_NAMELEN]; 295 char board_name[COMEDI_NAMELEN]; 296 int read_subdevice; 297 int write_subdevice; 298 int unused[30]; 299 }; 300 struct comedi_devconfig { 301 char board_name[COMEDI_NAMELEN]; 302 int options[COMEDI_NDEVCONFOPTS]; 303 }; 304 struct comedi_bufconfig { 305 unsigned int subdevice; 306 unsigned int flags; 307 unsigned int maximum_size; 308 unsigned int size; 309 unsigned int unused[4]; 310 }; 311 struct comedi_bufinfo { 312 unsigned int subdevice; 313 unsigned int bytes_read; 314 unsigned int buf_write_ptr; 315 unsigned int buf_read_ptr; 316 unsigned int buf_write_count; 317 unsigned int buf_read_count; 318 unsigned int bytes_written; 319 unsigned int unused[4]; 320 }; 321 #define __RANGE(a,b) ((((a) & 0xffff) << 16) | ((b) & 0xffff)) 322 #define RANGE_OFFSET(a) (((a) >> 16) & 0xffff) 323 #define RANGE_LENGTH(b) ((b) & 0xffff) 324 #define RF_UNIT(flags) ((flags) & 0xff) 325 #define RF_EXTERNAL 0x100 326 #define UNIT_volt 0 327 #define UNIT_mA 1 328 #define UNIT_none 2 329 #define COMEDI_MIN_SPEED 0xffffffffu 330 enum i8254_mode { 331 I8254_MODE0 = (0 << 1), 332 I8254_MODE1 = (1 << 1), 333 I8254_MODE2 = (2 << 1), 334 I8254_MODE3 = (3 << 1), 335 I8254_MODE4 = (4 << 1), 336 I8254_MODE5 = (5 << 1), 337 I8254_BCD = 1, 338 I8254_BINARY = 0 339 }; 340 #define NI_NAMES_BASE 0x8000u 341 #define _TERM_N(base,n,x) ((base) + ((x) & ((n) - 1))) 342 #define NI_PFI(x) _TERM_N(NI_NAMES_BASE, 64, x) 343 #define TRIGGER_LINE(x) _TERM_N(NI_PFI(- 1) + 1, 8, x) 344 #define NI_RTSI_BRD(x) _TERM_N(TRIGGER_LINE(- 1) + 1, 4, x) 345 #define NI_MAX_COUNTERS 8 346 #define NI_COUNTER_NAMES_BASE (NI_RTSI_BRD(- 1) + 1) 347 #define NI_CtrSource(x) _TERM_N(NI_COUNTER_NAMES_BASE, NI_MAX_COUNTERS, x) 348 #define NI_GATES_NAMES_BASE (NI_CtrSource(- 1) + 1) 349 #define NI_CtrGate(x) _TERM_N(NI_GATES_NAMES_BASE, NI_MAX_COUNTERS, x) 350 #define NI_CtrAux(x) _TERM_N(NI_CtrGate(- 1) + 1, NI_MAX_COUNTERS, x) 351 #define NI_CtrA(x) _TERM_N(NI_CtrAux(- 1) + 1, NI_MAX_COUNTERS, x) 352 #define NI_CtrB(x) _TERM_N(NI_CtrA(- 1) + 1, NI_MAX_COUNTERS, x) 353 #define NI_CtrZ(x) _TERM_N(NI_CtrB(- 1) + 1, NI_MAX_COUNTERS, x) 354 #define NI_GATES_NAMES_MAX NI_CtrZ(- 1) 355 #define NI_CtrArmStartTrigger(x) _TERM_N(NI_CtrZ(- 1) + 1, NI_MAX_COUNTERS, x) 356 #define NI_CtrInternalOutput(x) _TERM_N(NI_CtrArmStartTrigger(- 1) + 1, NI_MAX_COUNTERS, x) 357 #define NI_CtrOut(x) _TERM_N(NI_CtrInternalOutput(- 1) + 1, NI_MAX_COUNTERS, x) 358 #define NI_CtrSampleClock(x) _TERM_N(NI_CtrOut(- 1) + 1, NI_MAX_COUNTERS, x) 359 #define NI_COUNTER_NAMES_MAX NI_CtrSampleClock(- 1) 360 enum ni_common_signal_names { 361 PXI_Star = NI_COUNTER_NAMES_MAX + 1, 362 PXI_Clk10, 363 PXIe_Clk100, 364 NI_AI_SampleClock, 365 NI_AI_SampleClockTimebase, 366 NI_AI_StartTrigger, 367 NI_AI_ReferenceTrigger, 368 NI_AI_ConvertClock, 369 NI_AI_ConvertClockTimebase, 370 NI_AI_PauseTrigger, 371 NI_AI_HoldCompleteEvent, 372 NI_AI_HoldComplete, 373 NI_AI_ExternalMUXClock, 374 NI_AI_STOP, 375 NI_AO_SampleClock, 376 NI_AO_SampleClockTimebase, 377 NI_AO_StartTrigger, 378 NI_AO_PauseTrigger, 379 NI_DI_SampleClock, 380 NI_DI_SampleClockTimebase, 381 NI_DI_StartTrigger, 382 NI_DI_ReferenceTrigger, 383 NI_DI_PauseTrigger, 384 NI_DI_InputBufferFull, 385 NI_DI_ReadyForStartEvent, 386 NI_DI_ReadyForTransferEventBurst, 387 NI_DI_ReadyForTransferEventPipelined, 388 NI_DO_SampleClock, 389 NI_DO_SampleClockTimebase, 390 NI_DO_StartTrigger, 391 NI_DO_PauseTrigger, 392 NI_DO_OutputBufferFull, 393 NI_DO_DataActiveEvent, 394 NI_DO_ReadyForStartEvent, 395 NI_DO_ReadyForTransferEvent, 396 NI_MasterTimebase, 397 NI_20MHzTimebase, 398 NI_80MHzTimebase, 399 NI_100MHzTimebase, 400 NI_200MHzTimebase, 401 NI_100kHzTimebase, 402 NI_10MHzRefClock, 403 NI_FrequencyOutput, 404 NI_ChangeDetectionEvent, 405 NI_AnalogComparisonEvent, 406 NI_WatchdogExpiredEvent, 407 NI_WatchdogExpirationTrigger, 408 NI_SCXI_Trig1, 409 NI_LogicLow, 410 NI_LogicHigh, 411 NI_ExternalStrobe, 412 NI_PFI_DO, 413 NI_CaseGround, 414 NI_RGOUT0, 415 _NI_NAMES_MAX_PLUS_1, 416 NI_NUM_NAMES = _NI_NAMES_MAX_PLUS_1 - NI_NAMES_BASE, 417 }; 418 #define NI_USUAL_PFI_SELECT(x) (((x) < 10) ? (0x1 + (x)) : (0xb + (x))) 419 #define NI_USUAL_RTSI_SELECT(x) (((x) < 7) ? (0xb + (x)) : 0x1b) 420 #define NI_GPCT_COUNTING_MODE_SHIFT 16 421 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20 422 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 423 enum ni_gpct_mode_bits { 424 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, 425 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, 426 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, 427 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, 428 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, 429 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, 430 NI_GPCT_STOP_MODE_MASK = 0x60, 431 NI_GPCT_STOP_ON_GATE_BITS = 0x00, 432 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, 433 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, 434 NI_GPCT_LOAD_B_SELECT_BIT = 0x80, 435 NI_GPCT_OUTPUT_MODE_MASK = 0x300, 436 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, 437 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, 438 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, 439 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, 440 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, 441 NI_GPCT_DISARM_AT_TC_BITS = 0x400, 442 NI_GPCT_DISARM_AT_GATE_BITS = 0x800, 443 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, 444 NI_GPCT_LOADING_ON_TC_BIT = 0x1000, 445 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, 446 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, 447 NI_GPCT_COUNTING_MODE_NORMAL_BITS = 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, 448 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, 449 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, 450 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, 451 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, 452 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, 453 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 454 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, 455 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, 456 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, 457 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, 458 NI_GPCT_INDEX_ENABLE_BIT = 0x400000, 459 NI_GPCT_COUNTING_DIRECTION_MASK = 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 460 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 461 NI_GPCT_COUNTING_DIRECTION_UP_BITS = 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 462 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 463 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, 464 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, 465 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, 466 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, 467 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, 468 NI_GPCT_OR_GATE_BIT = 0x10000000, 469 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 470 }; 471 enum ni_gpct_clock_source_bits { 472 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, 473 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, 474 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, 475 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, 476 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, 477 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, 478 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, 479 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, 480 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, 481 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, 482 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, 483 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, 484 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, 485 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, 486 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, 487 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 488 }; 489 #define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x) (0x10 + (x)) 490 #define NI_GPCT_RTSI_CLOCK_SRC_BITS(x) (0x18 + (x)) 491 #define NI_GPCT_PFI_CLOCK_SRC_BITS(x) (0x20 + (x)) 492 enum ni_gpct_gate_select { 493 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, 494 NI_GPCT_AI_START2_GATE_SELECT = 0x12, 495 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, 496 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, 497 NI_GPCT_AI_START1_GATE_SELECT = 0x1c, 498 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, 499 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, 500 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, 501 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, 502 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, 503 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, 504 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, 505 NI_GPCT_DISABLED_GATE_SELECT = 0x8000, 506 }; 507 #define NI_GPCT_GATE_PIN_GATE_SELECT(x) (0x102 + (x)) 508 #define NI_GPCT_RTSI_GATE_SELECT(x) NI_USUAL_RTSI_SELECT(x) 509 #define NI_GPCT_PFI_GATE_SELECT(x) NI_USUAL_PFI_SELECT(x) 510 #define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x) (0x202 + (x)) 511 enum ni_gpct_other_index { 512 NI_GPCT_SOURCE_ENCODER_A, 513 NI_GPCT_SOURCE_ENCODER_B, 514 NI_GPCT_SOURCE_ENCODER_Z 515 }; 516 enum ni_gpct_other_select { 517 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, 518 }; 519 #define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x) 520 enum ni_gpct_arm_source { 521 NI_GPCT_ARM_IMMEDIATE = 0x0, 522 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, 523 NI_GPCT_HW_ARM = 0x1000, 524 NI_GPCT_ARM_UNKNOWN = NI_GPCT_HW_ARM, 525 }; 526 enum ni_gpct_filter_select { 527 NI_GPCT_FILTER_OFF = 0x0, 528 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, 529 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, 530 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, 531 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, 532 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, 533 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 534 }; 535 enum ni_pfi_filter_select { 536 NI_PFI_FILTER_OFF = 0x0, 537 NI_PFI_FILTER_125ns = 0x1, 538 NI_PFI_FILTER_6425ns = 0x2, 539 NI_PFI_FILTER_2550us = 0x3 540 }; 541 enum ni_mio_clock_source { 542 NI_MIO_INTERNAL_CLOCK = 0, 543 NI_MIO_RTSI_CLOCK = 1, 544 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, 545 NI_MIO_PLL_PXI10_CLOCK = 3, 546 NI_MIO_PLL_RTSI0_CLOCK = 4 547 }; 548 #define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x)) 549 enum ni_rtsi_routing { 550 NI_RTSI_OUTPUT_ADR_START1 = 0, 551 NI_RTSI_OUTPUT_ADR_START2 = 1, 552 NI_RTSI_OUTPUT_SCLKG = 2, 553 NI_RTSI_OUTPUT_DACUPDN = 3, 554 NI_RTSI_OUTPUT_DA_START1 = 4, 555 NI_RTSI_OUTPUT_G_SRC0 = 5, 556 NI_RTSI_OUTPUT_G_GATE0 = 6, 557 NI_RTSI_OUTPUT_RGOUT0 = 7, 558 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, 559 NI_RTSI_OUTPUT_RTSI_OSC = 12 560 }; 561 #define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x)) 562 enum ni_pfi_routing { 563 NI_PFI_OUTPUT_PFI_DEFAULT = 0, 564 NI_PFI_OUTPUT_AI_START1 = 1, 565 NI_PFI_OUTPUT_AI_START2 = 2, 566 NI_PFI_OUTPUT_AI_CONVERT = 3, 567 NI_PFI_OUTPUT_G_SRC1 = 4, 568 NI_PFI_OUTPUT_G_GATE1 = 5, 569 NI_PFI_OUTPUT_AO_UPDATE_N = 6, 570 NI_PFI_OUTPUT_AO_START1 = 7, 571 NI_PFI_OUTPUT_AI_START_PULSE = 8, 572 NI_PFI_OUTPUT_G_SRC0 = 9, 573 NI_PFI_OUTPUT_G_GATE0 = 10, 574 NI_PFI_OUTPUT_EXT_STROBE = 11, 575 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, 576 NI_PFI_OUTPUT_GOUT0 = 13, 577 NI_PFI_OUTPUT_GOUT1 = 14, 578 NI_PFI_OUTPUT_FREQ_OUT = 15, 579 NI_PFI_OUTPUT_PFI_DO = 16, 580 NI_PFI_OUTPUT_I_ATRIG = 17, 581 NI_PFI_OUTPUT_RTSI0 = 18, 582 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, 583 NI_PFI_OUTPUT_SCXI_TRIG1 = 27, 584 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, 585 NI_PFI_OUTPUT_CDI_SAMPLE = 29, 586 NI_PFI_OUTPUT_CDO_UPDATE = 30 587 }; 588 #define NI_PFI_OUTPUT_RTSI(x) (NI_PFI_OUTPUT_RTSI0 + (x)) 589 enum ni_660x_pfi_routing { 590 NI_660X_PFI_OUTPUT_COUNTER = 1, 591 NI_660X_PFI_OUTPUT_DIO = 2, 592 }; 593 #define NI_EXT_PFI(x) (NI_USUAL_PFI_SELECT(x) - 1) 594 #define NI_EXT_RTSI(x) (NI_USUAL_RTSI_SELECT(x) - 1) 595 enum ni_m_series_cdio_scan_begin_src { 596 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, 597 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, 598 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, 599 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, 600 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, 601 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, 602 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, 603 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, 604 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, 605 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 606 }; 607 #define NI_CDIO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x) 608 #define NI_CDIO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x) 609 #define NI_AO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x) 610 #define NI_AO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x) 611 enum ni_freq_out_clock_source_bits { 612 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, 613 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC 614 }; 615 enum amplc_dio_clock_source { 616 AMPLC_DIO_CLK_CLKN, 617 AMPLC_DIO_CLK_10MHZ, 618 AMPLC_DIO_CLK_1MHZ, 619 AMPLC_DIO_CLK_100KHZ, 620 AMPLC_DIO_CLK_10KHZ, 621 AMPLC_DIO_CLK_1KHZ, 622 AMPLC_DIO_CLK_OUTNM1, 623 AMPLC_DIO_CLK_EXT, 624 AMPLC_DIO_CLK_VCC, 625 AMPLC_DIO_CLK_GND, 626 AMPLC_DIO_CLK_PAT_PRESENT, 627 AMPLC_DIO_CLK_20MHZ 628 }; 629 enum amplc_dio_ts_clock_src { 630 AMPLC_DIO_TS_CLK_1GHZ, 631 AMPLC_DIO_TS_CLK_1MHZ, 632 AMPLC_DIO_TS_CLK_1KHZ 633 }; 634 enum amplc_dio_gate_source { 635 AMPLC_DIO_GAT_VCC, 636 AMPLC_DIO_GAT_GND, 637 AMPLC_DIO_GAT_GATN, 638 AMPLC_DIO_GAT_NOUTNM2, 639 AMPLC_DIO_GAT_RESERVED4, 640 AMPLC_DIO_GAT_RESERVED5, 641 AMPLC_DIO_GAT_RESERVED6, 642 AMPLC_DIO_GAT_RESERVED7, 643 AMPLC_DIO_GAT_NGATN = 6, 644 AMPLC_DIO_GAT_OUTNM2, 645 AMPLC_DIO_GAT_PAT_PRESENT, 646 AMPLC_DIO_GAT_PAT_OCCURRED, 647 AMPLC_DIO_GAT_PAT_GONE, 648 AMPLC_DIO_GAT_NPAT_PRESENT, 649 AMPLC_DIO_GAT_NPAT_OCCURRED, 650 AMPLC_DIO_GAT_NPAT_GONE 651 }; 652 enum ke_counter_clock_source { 653 KE_CLK_20MHZ, 654 KE_CLK_4MHZ, 655 KE_CLK_EXT 656 }; 657 #endif 658