1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_NPU_H_ 20 #define _MSM_NPU_H_ 21 #include <linux/types.h> 22 #define MSM_NPU_IOCTL_MAGIC 'n' 23 #define MSM_NPU_GET_INFO _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl) 24 #define MSM_NPU_MAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl) 25 #define MSM_NPU_UNMAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl) 26 #define MSM_NPU_LOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl) 27 #define MSM_NPU_UNLOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl) 28 #define MSM_NPU_EXEC_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl) 29 #define MSM_NPU_LOAD_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2) 30 #define MSM_NPU_EXEC_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2) 31 #define MSM_NPU_RECEIVE_EVENT _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event) 32 #define MSM_NPU_SET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property) 33 #define MSM_NPU_GET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property) 34 #define MSM_NPU_EVENT_TYPE_START 0x10000000 35 #define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1) 36 #define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2) 37 #define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3) 38 #define MSM_NPU_MAX_INPUT_LAYER_NUM 8 39 #define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4 40 #define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM + MSM_NPU_MAX_OUTPUT_LAYER_NUM) 41 #define MSM_NPU_PROP_ID_START 0x100 42 #define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0) 43 #define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1) 44 #define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2) 45 #define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3) 46 #define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4) 47 #define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5) 48 #define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6) 49 #define MSM_NPU_FW_PROP_ID_START 0x1000 50 #define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0) 51 #define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1) 52 #define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2) 53 #define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3) 54 #define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4) 55 #define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5) 56 #define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1 57 #define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2 58 #define MSM_NPU_FEATURE_DSP_SID_MAPPED 0x8 59 #define PROP_PARAM_MAX_SIZE 8 60 struct msm_npu_patch_info { 61 uint32_t chunk_id; 62 uint16_t instruction_size_in_bytes; 63 uint16_t variable_size_in_bits; 64 uint16_t shift_value_in_bits; 65 uint32_t loc_offset; 66 }; 67 struct msm_npu_layer { 68 uint32_t layer_id; 69 struct msm_npu_patch_info patch_info; 70 int32_t buf_hdl; 71 uint32_t buf_size; 72 uint64_t buf_phys_addr; 73 }; 74 struct msm_npu_patch_info_v2 { 75 uint32_t value; 76 uint32_t chunk_id; 77 uint32_t instruction_size_in_bytes; 78 uint32_t variable_size_in_bits; 79 uint32_t shift_value_in_bits; 80 uint32_t loc_offset; 81 }; 82 struct msm_npu_patch_buf_info { 83 uint64_t buf_phys_addr; 84 uint32_t buf_id; 85 }; 86 struct msm_npu_map_buf_ioctl { 87 int32_t buf_ion_hdl; 88 uint32_t size; 89 uint64_t npu_phys_addr; 90 }; 91 struct msm_npu_unmap_buf_ioctl { 92 int32_t buf_ion_hdl; 93 uint64_t npu_phys_addr; 94 }; 95 struct msm_npu_get_info_ioctl { 96 uint32_t firmware_version; 97 uint32_t flags; 98 }; 99 struct msm_npu_load_network_ioctl { 100 int32_t buf_ion_hdl; 101 uint64_t buf_phys_addr; 102 uint32_t buf_size; 103 uint32_t first_block_size; 104 uint32_t flags; 105 uint32_t network_hdl; 106 uint32_t priority; 107 uint32_t perf_mode; 108 }; 109 struct msm_npu_load_network_ioctl_v2 { 110 uint64_t buf_phys_addr; 111 uint64_t patch_info; 112 int32_t buf_ion_hdl; 113 uint32_t buf_size; 114 uint32_t first_block_size; 115 uint32_t flags; 116 uint32_t network_hdl; 117 uint32_t priority; 118 uint32_t perf_mode; 119 uint32_t num_layers; 120 uint32_t patch_info_num; 121 uint32_t reserved; 122 }; 123 struct msm_npu_unload_network_ioctl { 124 uint32_t network_hdl; 125 }; 126 struct msm_npu_exec_network_ioctl { 127 uint32_t network_hdl; 128 uint32_t input_layer_num; 129 struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM]; 130 uint32_t output_layer_num; 131 struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM]; 132 uint32_t patching_required; 133 uint32_t async; 134 uint32_t flags; 135 }; 136 struct msm_npu_exec_network_ioctl_v2 { 137 uint64_t stats_buf_addr; 138 uint64_t patch_buf_info; 139 uint32_t network_hdl; 140 uint32_t async; 141 uint32_t flags; 142 uint32_t stats_buf_size; 143 uint32_t patch_buf_info_num; 144 uint32_t reserved; 145 }; 146 struct msm_npu_event_execute_done { 147 uint32_t network_hdl; 148 int32_t exec_result; 149 }; 150 struct msm_npu_event_execute_v2_done { 151 uint32_t network_hdl; 152 int32_t exec_result; 153 uint32_t stats_buf_size; 154 }; 155 struct msm_npu_event_ssr { 156 uint32_t network_hdl; 157 }; 158 struct msm_npu_event { 159 uint32_t type; 160 union { 161 struct msm_npu_event_execute_done exec_done; 162 struct msm_npu_event_execute_v2_done exec_v2_done; 163 struct msm_npu_event_ssr ssr; 164 uint8_t data[128]; 165 } u; 166 uint32_t reserved[4]; 167 }; 168 struct msm_npu_property { 169 uint32_t prop_id; 170 uint32_t num_of_params; 171 uint32_t network_hdl; 172 uint32_t prop_param[PROP_PARAM_MAX_SIZE]; 173 }; 174 #endif 175