1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _SDE_DRM_H_ 8 #define _SDE_DRM_H_ 9 #include "drm.h" 10 #define SDE_MAX_PLANES 4 11 #define SDE_MAX_DE_CURVES 3 12 #define FILTER_EDGE_DIRECTED_2D 0x0 13 #define FILTER_CIRCULAR_2D 0x1 14 #define FILTER_SEPARABLE_1D 0x2 15 #define FILTER_BILINEAR 0x3 16 #define FILTER_ALPHA_DROP_REPEAT 0x0 17 #define FILTER_ALPHA_BILINEAR 0x1 18 #define FILTER_ALPHA_2D 0x3 19 #define FILTER_BLEND_CIRCULAR_2D 0x0 20 #define FILTER_BLEND_SEPARABLE_1D 0x1 21 #define SCALER_LUT_SWAP 0x1 22 #define SCALER_LUT_DIR_WR 0x2 23 #define SCALER_LUT_Y_CIR_WR 0x4 24 #define SCALER_LUT_UV_CIR_WR 0x8 25 #define SCALER_LUT_Y_SEP_WR 0x10 26 #define SCALER_LUT_UV_SEP_WR 0x20 27 #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 28 #define SDE_DRM_BLEND_OP_OPAQUE 1 29 #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 30 #define SDE_DRM_BLEND_OP_COVERAGE 3 31 #define SDE_DRM_BLEND_OP_LAYER_COLOR 4 32 #define SDE_DRM_BLEND_OP_MAX 5 33 #define SDE_DRM_DEINTERLACE 0 34 #define SDE_DRM_BITMASK_COUNT 64 35 #define SDE_DRM_FB_NON_SEC 0 36 #define SDE_DRM_FB_SEC 1 37 #define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 38 #define SDE_DRM_FB_SEC_DIR_TRANS 3 39 #define SDE_DRM_SEC_NON_SEC 0 40 #define SDE_DRM_SEC_ONLY 1 41 struct sde_drm_pix_ext_v1 { 42 int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; 43 int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; 44 int32_t left_ftch[SDE_MAX_PLANES]; 45 int32_t right_ftch[SDE_MAX_PLANES]; 46 int32_t top_ftch[SDE_MAX_PLANES]; 47 int32_t btm_ftch[SDE_MAX_PLANES]; 48 int32_t left_rpt[SDE_MAX_PLANES]; 49 int32_t right_rpt[SDE_MAX_PLANES]; 50 int32_t top_rpt[SDE_MAX_PLANES]; 51 int32_t btm_rpt[SDE_MAX_PLANES]; 52 }; 53 struct sde_drm_scaler_v1 { 54 struct sde_drm_pix_ext_v1 pe; 55 int32_t init_phase_x[SDE_MAX_PLANES]; 56 int32_t phase_step_x[SDE_MAX_PLANES]; 57 int32_t init_phase_y[SDE_MAX_PLANES]; 58 int32_t phase_step_y[SDE_MAX_PLANES]; 59 uint32_t horz_filter[SDE_MAX_PLANES]; 60 uint32_t vert_filter[SDE_MAX_PLANES]; 61 }; 62 struct sde_drm_de_v1 { 63 uint32_t enable; 64 int16_t sharpen_level1; 65 int16_t sharpen_level2; 66 uint16_t clip; 67 uint16_t limit; 68 uint16_t thr_quiet; 69 uint16_t thr_dieout; 70 uint16_t thr_low; 71 uint16_t thr_high; 72 uint16_t prec_shift; 73 int16_t adjust_a[SDE_MAX_DE_CURVES]; 74 int16_t adjust_b[SDE_MAX_DE_CURVES]; 75 int16_t adjust_c[SDE_MAX_DE_CURVES]; 76 }; 77 #define SDE_DYN_EXP_DISABLE 0x1 78 #define SDE_DRM_QSEED3LITE 79 #define SDE_DRM_QSEED4 80 #define SDE_DRM_INLINE_PREDOWNSCALE 81 struct sde_drm_scaler_v2 { 82 uint32_t enable; 83 uint32_t dir_en; 84 struct sde_drm_pix_ext_v1 pe; 85 uint32_t horz_decimate; 86 uint32_t vert_decimate; 87 int32_t init_phase_x[SDE_MAX_PLANES]; 88 int32_t phase_step_x[SDE_MAX_PLANES]; 89 int32_t init_phase_y[SDE_MAX_PLANES]; 90 int32_t phase_step_y[SDE_MAX_PLANES]; 91 uint32_t preload_x[SDE_MAX_PLANES]; 92 uint32_t preload_y[SDE_MAX_PLANES]; 93 uint32_t src_width[SDE_MAX_PLANES]; 94 uint32_t src_height[SDE_MAX_PLANES]; 95 uint32_t dst_width; 96 uint32_t dst_height; 97 uint32_t y_rgb_filter_cfg; 98 uint32_t uv_filter_cfg; 99 uint32_t alpha_filter_cfg; 100 uint32_t blend_cfg; 101 uint32_t lut_flag; 102 uint32_t dir_lut_idx; 103 uint32_t y_rgb_cir_lut_idx; 104 uint32_t uv_cir_lut_idx; 105 uint32_t y_rgb_sep_lut_idx; 106 uint32_t uv_sep_lut_idx; 107 struct sde_drm_de_v1 de; 108 uint32_t dir_weight; 109 uint32_t unsharp_mask_blend; 110 uint32_t de_blend; 111 uint32_t flags; 112 uint32_t pre_downscale_x_0; 113 uint32_t pre_downscale_x_1; 114 uint32_t pre_downscale_y_0; 115 uint32_t pre_downscale_y_1; 116 }; 117 #define SDE_MAX_DS_COUNT 2 118 #define SDE_DRM_DESTSCALER_ENABLE 0x1 119 #define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 120 #define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 121 #define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 122 struct sde_drm_dest_scaler_cfg { 123 uint32_t flags; 124 uint32_t index; 125 uint32_t lm_width; 126 uint32_t lm_height; 127 uint64_t scaler_cfg; 128 }; 129 struct sde_drm_dest_scaler_data { 130 uint32_t num_dest_scaler; 131 struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; 132 }; 133 #define SDE_CSC_MATRIX_COEFF_SIZE 9 134 #define SDE_CSC_CLAMP_SIZE 6 135 #define SDE_CSC_BIAS_SIZE 3 136 struct sde_drm_csc_v1 { 137 int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; 138 uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; 139 uint32_t post_bias[SDE_CSC_BIAS_SIZE]; 140 uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; 141 uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; 142 }; 143 struct sde_drm_color { 144 uint32_t color_0; 145 uint32_t color_1; 146 uint32_t color_2; 147 uint32_t color_3; 148 }; 149 #define SDE_MAX_DIM_LAYERS 7 150 #define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 151 #define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 152 struct sde_drm_dim_layer_cfg { 153 uint32_t flags; 154 uint32_t stage; 155 struct sde_drm_color color_fill; 156 struct drm_clip_rect rect; 157 }; 158 struct sde_drm_dim_layer_v1 { 159 uint32_t num_layers; 160 struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; 161 }; 162 #define SDE_DRM_WB_CFG 0x1 163 #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0) 164 struct sde_drm_wb_cfg { 165 uint32_t flags; 166 uint32_t connector_id; 167 uint32_t count_modes; 168 uint64_t modes; 169 }; 170 #define SDE_MAX_ROI_V1 4 171 struct sde_drm_roi_v1 { 172 uint32_t num_rects; 173 struct drm_clip_rect roi[SDE_MAX_ROI_V1]; 174 }; 175 #define SDE_MODE_DPMS_ON 0 176 #define SDE_MODE_DPMS_LP1 1 177 #define SDE_MODE_DPMS_LP2 2 178 #define SDE_MODE_DPMS_STANDBY 3 179 #define SDE_MODE_DPMS_SUSPEND 4 180 #define SDE_MODE_DPMS_OFF 5 181 #define SDE_RECOVERY_SUCCESS 0 182 #define SDE_RECOVERY_CAPTURE 1 183 #define SDE_RECOVERY_HARD_RESET 2 184 #define DRM_FORMAT_MOD_QCOM_FSC_TILE fourcc_mod_code(QCOM, 0x10) 185 #endif 186