1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __UAPI_CAM_DEFS_H__ 8 #define __UAPI_CAM_DEFS_H__ 9 #include <linux/videodev2.h> 10 #include <linux/types.h> 11 #include <linux/ioctl.h> 12 #define CAM_COMMON_OPCODE_BASE 0x100 13 #define CAM_QUERY_CAP (CAM_COMMON_OPCODE_BASE + 0x1) 14 #define CAM_ACQUIRE_DEV (CAM_COMMON_OPCODE_BASE + 0x2) 15 #define CAM_START_DEV (CAM_COMMON_OPCODE_BASE + 0x3) 16 #define CAM_STOP_DEV (CAM_COMMON_OPCODE_BASE + 0x4) 17 #define CAM_CONFIG_DEV (CAM_COMMON_OPCODE_BASE + 0x5) 18 #define CAM_RELEASE_DEV (CAM_COMMON_OPCODE_BASE + 0x6) 19 #define CAM_SD_SHUTDOWN (CAM_COMMON_OPCODE_BASE + 0x7) 20 #define CAM_FLUSH_REQ (CAM_COMMON_OPCODE_BASE + 0x8) 21 #define CAM_COMMON_OPCODE_MAX (CAM_COMMON_OPCODE_BASE + 0x9) 22 #define CAM_COMMON_OPCODE_BASE_v2 0x150 23 #define CAM_ACQUIRE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x1) 24 #define CAM_RELEASE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x2) 25 #define CAM_DUMP_REQ (CAM_COMMON_OPCODE_BASE_v2 + 0x3) 26 #define CAM_EXT_OPCODE_BASE 0x200 27 #define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) 28 #define CAM_HANDLE_USER_POINTER 1 29 #define CAM_HANDLE_MEM_HANDLE 2 30 #define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_MASK 0xFFFFFF00 31 #define CAM_GENERIC_BLOB_CMDBUFFER_SIZE_SHIFT 8 32 #define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_MASK 0xFF 33 #define CAM_GENERIC_BLOB_CMDBUFFER_TYPE_SHIFT 0 34 #define CAM_CMD_BUF_DMI 0x1 35 #define CAM_CMD_BUF_DMI16 0x2 36 #define CAM_CMD_BUF_DMI32 0x3 37 #define CAM_CMD_BUF_DMI64 0x4 38 #define CAM_CMD_BUF_DIRECT 0x5 39 #define CAM_CMD_BUF_INDIRECT 0x6 40 #define CAM_CMD_BUF_I2C 0x7 41 #define CAM_CMD_BUF_FW 0x8 42 #define CAM_CMD_BUF_GENERIC 0x9 43 #define CAM_CMD_BUF_LEGACY 0xA 44 #define CAM_UBWC_CFG_VERSION_1 1 45 #define CAM_UBWC_CFG_VERSION_2 2 46 #define CAM_MAX_ACQ_RES 5 47 #define CAM_MAX_HW_SPLIT 3 48 enum flush_type_t { 49 CAM_FLUSH_TYPE_REQ, 50 CAM_FLUSH_TYPE_ALL, 51 CAM_FLUSH_TYPE_MAX 52 }; 53 struct cam_control { 54 uint32_t op_code; 55 uint32_t size; 56 uint32_t handle_type; 57 uint32_t reserved; 58 uint64_t handle; 59 }; 60 #define VIDIOC_CAM_CONTROL _IOWR('V', BASE_VIDIOC_PRIVATE, struct cam_control) 61 struct cam_hw_version { 62 uint32_t major; 63 uint32_t minor; 64 uint32_t incr; 65 uint32_t reserved; 66 }; 67 struct cam_iommu_handle { 68 int32_t non_secure; 69 int32_t secure; 70 }; 71 #define CAM_SECURE_MODE_NON_SECURE 0 72 #define CAM_SECURE_MODE_SECURE 1 73 #define CAM_FORMAT_BASE 0 74 #define CAM_FORMAT_MIPI_RAW_6 1 75 #define CAM_FORMAT_MIPI_RAW_8 2 76 #define CAM_FORMAT_MIPI_RAW_10 3 77 #define CAM_FORMAT_MIPI_RAW_12 4 78 #define CAM_FORMAT_MIPI_RAW_14 5 79 #define CAM_FORMAT_MIPI_RAW_16 6 80 #define CAM_FORMAT_MIPI_RAW_20 7 81 #define CAM_FORMAT_QTI_RAW_8 8 82 #define CAM_FORMAT_QTI_RAW_10 9 83 #define CAM_FORMAT_QTI_RAW_12 10 84 #define CAM_FORMAT_QTI_RAW_14 11 85 #define CAM_FORMAT_PLAIN8 12 86 #define CAM_FORMAT_PLAIN16_8 13 87 #define CAM_FORMAT_PLAIN16_10 14 88 #define CAM_FORMAT_PLAIN16_12 15 89 #define CAM_FORMAT_PLAIN16_14 16 90 #define CAM_FORMAT_PLAIN16_16 17 91 #define CAM_FORMAT_PLAIN32_20 18 92 #define CAM_FORMAT_PLAIN64 19 93 #define CAM_FORMAT_PLAIN128 20 94 #define CAM_FORMAT_ARGB 21 95 #define CAM_FORMAT_ARGB_10 22 96 #define CAM_FORMAT_ARGB_12 23 97 #define CAM_FORMAT_ARGB_14 24 98 #define CAM_FORMAT_DPCM_10_6_10 25 99 #define CAM_FORMAT_DPCM_10_8_10 26 100 #define CAM_FORMAT_DPCM_12_6_12 27 101 #define CAM_FORMAT_DPCM_12_8_12 28 102 #define CAM_FORMAT_DPCM_14_8_14 29 103 #define CAM_FORMAT_DPCM_14_10_14 30 104 #define CAM_FORMAT_NV21 31 105 #define CAM_FORMAT_NV12 32 106 #define CAM_FORMAT_TP10 33 107 #define CAM_FORMAT_YUV422 34 108 #define CAM_FORMAT_PD8 35 109 #define CAM_FORMAT_PD10 36 110 #define CAM_FORMAT_UBWC_NV12 37 111 #define CAM_FORMAT_UBWC_NV12_4R 38 112 #define CAM_FORMAT_UBWC_TP10 39 113 #define CAM_FORMAT_UBWC_P010 40 114 #define CAM_FORMAT_PLAIN8_SWAP 41 115 #define CAM_FORMAT_PLAIN8_10 42 116 #define CAM_FORMAT_PLAIN8_10_SWAP 43 117 #define CAM_FORMAT_YV12 44 118 #define CAM_FORMAT_Y_ONLY 45 119 #define CAM_FORMAT_DPCM_12_10_12 46 120 #define CAM_FORMAT_PLAIN32 47 121 #define CAM_FORMAT_ARGB_16 48 122 #define CAM_FORMAT_MAX 49 123 #define CAM_ROTATE_CW_0_DEGREE 0 124 #define CAM_ROTATE_CW_90_DEGREE 1 125 #define CAM_RORATE_CW_180_DEGREE 2 126 #define CAM_ROTATE_CW_270_DEGREE 3 127 #define CAM_COLOR_SPACE_BASE 0 128 #define CAM_COLOR_SPACE_BT601_FULL 1 129 #define CAM_COLOR_SPACE_BT601625 2 130 #define CAM_COLOR_SPACE_BT601525 3 131 #define CAM_COLOR_SPACE_BT709 4 132 #define CAM_COLOR_SPACE_DEPTH 5 133 #define CAM_COLOR_SPACE_MAX 6 134 #define CAM_BUF_INPUT 1 135 #define CAM_BUF_OUTPUT 2 136 #define CAM_BUF_IN_OUT 3 137 #define CAM_PACKET_DEV_BASE 0 138 #define CAM_PACKET_DEV_IMG_SENSOR 1 139 #define CAM_PACKET_DEV_ACTUATOR 2 140 #define CAM_PACKET_DEV_COMPANION 3 141 #define CAM_PACKET_DEV_EEPOM 4 142 #define CAM_PACKET_DEV_CSIPHY 5 143 #define CAM_PACKET_DEV_OIS 6 144 #define CAM_PACKET_DEV_FLASH 7 145 #define CAM_PACKET_DEV_FD 8 146 #define CAM_PACKET_DEV_JPEG_ENC 9 147 #define CAM_PACKET_DEV_JPEG_DEC 10 148 #define CAM_PACKET_DEV_VFE 11 149 #define CAM_PACKET_DEV_CPP 12 150 #define CAM_PACKET_DEV_CSID 13 151 #define CAM_PACKET_DEV_ISPIF 14 152 #define CAM_PACKET_DEV_IFE 15 153 #define CAM_PACKET_DEV_ICP 16 154 #define CAM_PACKET_DEV_LRME 17 155 #define CAM_PACKET_DEV_MAX 18 156 #define CAM_REG_DUMP_BASE_TYPE_ISP_LEFT 1 157 #define CAM_REG_DUMP_BASE_TYPE_ISP_RIGHT 2 158 #define CAM_REG_DUMP_BASE_TYPE_CAMNOC 3 159 #define CAM_REG_DUMP_READ_TYPE_CONT_RANGE 1 160 #define CAM_REG_DUMP_READ_TYPE_DMI 2 161 #define CAM_REG_DUMP_DMI_CONFIG_MAX 5 162 #define CAM_PACKET_MAX_PLANES 3 163 struct cam_plane_cfg { 164 uint32_t width; 165 uint32_t height; 166 uint32_t plane_stride; 167 uint32_t slice_height; 168 uint32_t meta_stride; 169 uint32_t meta_size; 170 uint32_t meta_offset; 171 uint32_t packer_config; 172 uint32_t mode_config; 173 uint32_t tile_config; 174 uint32_t h_init; 175 uint32_t v_init; 176 }; 177 struct cam_ubwc_plane_cfg_v1 { 178 uint32_t port_type; 179 uint32_t meta_stride; 180 uint32_t meta_size; 181 uint32_t meta_offset; 182 uint32_t packer_config; 183 uint32_t mode_config_0; 184 uint32_t mode_config_1; 185 uint32_t tile_config; 186 uint32_t h_init; 187 uint32_t v_init; 188 }; 189 struct cam_ubwc_plane_cfg_v2 { 190 uint32_t port_type; 191 uint32_t meta_stride; 192 uint32_t meta_size; 193 uint32_t meta_offset; 194 uint32_t packer_config; 195 uint32_t mode_config_0; 196 uint32_t mode_config_1; 197 uint32_t tile_config; 198 uint32_t h_init; 199 uint32_t v_init; 200 uint32_t static_ctrl; 201 uint32_t ctrl_2; 202 uint32_t stats_ctrl_2; 203 uint32_t lossy_threshold_0; 204 uint32_t lossy_threshold_1; 205 uint32_t lossy_var_offset; 206 uint32_t bandwidth_limit; 207 uint32_t reserved[3]; 208 }; 209 struct cam_cmd_buf_desc { 210 int32_t mem_handle; 211 uint32_t offset; 212 uint32_t size; 213 uint32_t length; 214 uint32_t type; 215 uint32_t meta_data; 216 }; 217 struct cam_buf_io_cfg { 218 int32_t mem_handle[CAM_PACKET_MAX_PLANES]; 219 uint32_t offsets[CAM_PACKET_MAX_PLANES]; 220 struct cam_plane_cfg planes[CAM_PACKET_MAX_PLANES]; 221 uint32_t format; 222 uint32_t color_space; 223 uint32_t color_pattern; 224 uint32_t bpp; 225 uint32_t rotation; 226 uint32_t resource_type; 227 int32_t fence; 228 int32_t early_fence; 229 struct cam_cmd_buf_desc aux_cmd_buf; 230 uint32_t direction; 231 uint32_t batch_size; 232 uint32_t subsample_pattern; 233 uint32_t subsample_period; 234 uint32_t framedrop_pattern; 235 uint32_t framedrop_period; 236 uint32_t flag; 237 uint32_t padding; 238 }; 239 struct cam_packet_header { 240 uint32_t op_code; 241 uint32_t size; 242 uint64_t request_id; 243 uint32_t flags; 244 uint32_t padding; 245 }; 246 struct cam_patch_desc { 247 int32_t dst_buf_hdl; 248 uint32_t dst_offset; 249 int32_t src_buf_hdl; 250 uint32_t src_offset; 251 }; 252 struct cam_packet { 253 struct cam_packet_header header; 254 uint32_t cmd_buf_offset; 255 uint32_t num_cmd_buf; 256 uint32_t io_configs_offset; 257 uint32_t num_io_configs; 258 uint32_t patch_offset; 259 uint32_t num_patches; 260 uint32_t kmd_cmd_buf_index; 261 uint32_t kmd_cmd_buf_offset; 262 uint64_t payload[1]; 263 }; 264 struct cam_release_dev_cmd { 265 int32_t session_handle; 266 int32_t dev_handle; 267 }; 268 struct cam_start_stop_dev_cmd { 269 int32_t session_handle; 270 int32_t dev_handle; 271 }; 272 struct cam_config_dev_cmd { 273 int32_t session_handle; 274 int32_t dev_handle; 275 uint64_t offset; 276 uint64_t packet_handle; 277 }; 278 struct cam_query_cap_cmd { 279 uint32_t size; 280 uint32_t handle_type; 281 uint64_t caps_handle; 282 }; 283 struct cam_acquire_dev_cmd { 284 int32_t session_handle; 285 int32_t dev_handle; 286 uint32_t handle_type; 287 uint32_t num_resources; 288 uint64_t resource_hdl; 289 }; 290 #define CAM_API_COMPAT_CONSTANT 0xFEFEFEFE 291 #define CAM_ACQUIRE_HW_STRUCT_VERSION_1 1 292 #define CAM_ACQUIRE_HW_STRUCT_VERSION_2 2 293 struct cam_acquire_hw_cmd_v1 { 294 uint32_t struct_version; 295 uint32_t reserved; 296 int32_t session_handle; 297 int32_t dev_handle; 298 uint32_t handle_type; 299 uint32_t data_size; 300 uint64_t resource_hdl; 301 }; 302 struct cam_acquired_hw_info { 303 uint32_t acquired_hw_id[CAM_MAX_ACQ_RES]; 304 uint32_t acquired_hw_path[CAM_MAX_ACQ_RES][CAM_MAX_HW_SPLIT]; 305 uint32_t valid_acquired_hw; 306 }; 307 struct cam_acquire_hw_cmd_v2 { 308 uint32_t struct_version; 309 uint32_t reserved; 310 int32_t session_handle; 311 int32_t dev_handle; 312 uint32_t handle_type; 313 uint32_t data_size; 314 uint64_t resource_hdl; 315 struct cam_acquired_hw_info hw_info; 316 }; 317 #define CAM_RELEASE_HW_STRUCT_VERSION_1 1 318 struct cam_release_hw_cmd_v1 { 319 uint32_t struct_version; 320 uint32_t reserved; 321 int32_t session_handle; 322 int32_t dev_handle; 323 }; 324 struct cam_flush_dev_cmd { 325 uint64_t version; 326 int32_t session_handle; 327 int32_t dev_handle; 328 uint32_t flush_type; 329 uint32_t reserved; 330 int64_t req_id; 331 }; 332 struct cam_ubwc_config { 333 uint32_t api_version; 334 uint32_t num_ports; 335 struct cam_ubwc_plane_cfg_v1 ubwc_plane_cfg[1][CAM_PACKET_MAX_PLANES - 1]; 336 }; 337 struct cam_ubwc_config_v2 { 338 uint32_t api_version; 339 uint32_t num_ports; 340 struct cam_ubwc_plane_cfg_v2 ubwc_plane_cfg[1][CAM_PACKET_MAX_PLANES - 1]; 341 }; 342 struct cam_cmd_mem_region_info { 343 int32_t mem_handle; 344 uint32_t offset; 345 uint32_t size; 346 uint32_t flags; 347 }; 348 struct cam_cmd_mem_regions { 349 uint32_t version; 350 uint32_t num_regions; 351 struct cam_cmd_mem_region_info map_info_array[1]; 352 }; 353 struct cam_reg_write_desc { 354 uint32_t offset; 355 uint32_t value; 356 }; 357 struct cam_reg_range_read_desc { 358 uint32_t offset; 359 uint32_t num_values; 360 }; 361 struct cam_dmi_read_desc { 362 uint32_t num_pre_writes; 363 uint32_t num_post_writes; 364 struct cam_reg_write_desc pre_read_config[CAM_REG_DUMP_DMI_CONFIG_MAX]; 365 struct cam_reg_range_read_desc dmi_data_read; 366 struct cam_reg_write_desc post_read_config[CAM_REG_DUMP_DMI_CONFIG_MAX]; 367 }; 368 struct cam_reg_read_info { 369 uint32_t type; 370 uint32_t reserved; 371 union { 372 struct cam_reg_range_read_desc reg_read; 373 struct cam_dmi_read_desc dmi_read; 374 }; 375 }; 376 struct cam_reg_dump_out_buffer { 377 uint64_t req_id; 378 uint32_t bytes_written; 379 uint32_t dump_data[1]; 380 }; 381 struct cam_reg_dump_desc { 382 uint32_t reg_base_type; 383 uint32_t dump_buffer_offset; 384 uint32_t dump_buffer_size; 385 uint32_t num_read_range; 386 struct cam_reg_read_info read_range[1]; 387 }; 388 struct cam_reg_dump_input_info { 389 uint32_t num_dump_sets; 390 uint32_t dump_set_offsets[1]; 391 }; 392 struct cam_dump_req_cmd { 393 uint64_t issue_req_id; 394 size_t offset; 395 uint32_t buf_handle; 396 uint32_t error_type; 397 int32_t session_handle; 398 int32_t link_hdl; 399 int32_t dev_handle; 400 }; 401 #endif 402