1 #ifndef _MSM_NPU_H_ 2 #define _MSM_NPU_H_ 3 4 /* ------------------------------------------------------------------------- 5 * Includes 6 * ------------------------------------------------------------------------- 7 */ 8 #include <linux/types.h> 9 10 /* ------------------------------------------------------------------------- 11 * Defines 12 * ------------------------------------------------------------------------- 13 */ 14 #define MSM_NPU_IOCTL_MAGIC 'n' 15 16 /* get npu info */ 17 #define MSM_NPU_GET_INFO \ 18 _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl) 19 20 /* map buf */ 21 #define MSM_NPU_MAP_BUF \ 22 _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl) 23 24 /* map buf */ 25 #define MSM_NPU_UNMAP_BUF \ 26 _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl) 27 28 /* load network */ 29 #define MSM_NPU_LOAD_NETWORK \ 30 _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl) 31 32 /* unload network */ 33 #define MSM_NPU_UNLOAD_NETWORK \ 34 _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl) 35 36 /* exec network */ 37 #define MSM_NPU_EXEC_NETWORK \ 38 _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl) 39 40 /* load network v2 */ 41 #define MSM_NPU_LOAD_NETWORK_V2 \ 42 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2) 43 44 /* exec network v2 */ 45 #define MSM_NPU_EXEC_NETWORK_V2 \ 46 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2) 47 48 /* receive event */ 49 #define MSM_NPU_RECEIVE_EVENT \ 50 _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event) 51 52 /* set property */ 53 #define MSM_NPU_SET_PROP \ 54 _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property) 55 56 /* get property */ 57 #define MSM_NPU_GET_PROP \ 58 _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property) 59 60 #define MSM_NPU_EVENT_TYPE_START 0x10000000 61 #define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1) 62 #define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2) 63 #define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3) 64 65 #define MSM_NPU_MAX_INPUT_LAYER_NUM 8 66 #define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4 67 #define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM +\ 68 MSM_NPU_MAX_OUTPUT_LAYER_NUM) 69 70 #define MSM_NPU_PROP_ID_START 0x100 71 #define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0) 72 #define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1) 73 #define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2) 74 #define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3) 75 #define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4) 76 #define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5) 77 #define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6) 78 79 #define MSM_NPU_FW_PROP_ID_START 0x1000 80 #define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0) 81 #define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1) 82 #define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2) 83 #define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3) 84 #define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4) 85 #define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5) 86 87 /* features supported by driver */ 88 #define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1 89 #define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2 90 #define MSM_NPU_FEATURE_DSP_SID_MAPPED 0x8 91 92 #define PROP_PARAM_MAX_SIZE 8 93 94 /* ------------------------------------------------------------------------- 95 * Data Structures 96 * ------------------------------------------------------------------------- 97 */ 98 struct msm_npu_patch_info { 99 /* chunk id */ 100 uint32_t chunk_id; 101 /* instruction size in bytes */ 102 uint16_t instruction_size_in_bytes; 103 /* variable size in bits */ 104 uint16_t variable_size_in_bits; 105 /* shift value in bits */ 106 uint16_t shift_value_in_bits; 107 /* location offset */ 108 uint32_t loc_offset; 109 }; 110 111 struct msm_npu_layer { 112 /* layer id */ 113 uint32_t layer_id; 114 /* patch information*/ 115 struct msm_npu_patch_info patch_info; 116 /* buffer handle */ 117 int32_t buf_hdl; 118 /* buffer size */ 119 uint32_t buf_size; 120 /* physical address */ 121 uint64_t buf_phys_addr; 122 }; 123 124 struct msm_npu_patch_info_v2 { 125 /* patch value */ 126 uint32_t value; 127 /* chunk id */ 128 uint32_t chunk_id; 129 /* instruction size in bytes */ 130 uint32_t instruction_size_in_bytes; 131 /* variable size in bits */ 132 uint32_t variable_size_in_bits; 133 /* shift value in bits */ 134 uint32_t shift_value_in_bits; 135 /* location offset */ 136 uint32_t loc_offset; 137 }; 138 139 struct msm_npu_patch_buf_info { 140 /* physical address to be patched */ 141 uint64_t buf_phys_addr; 142 /* buffer id */ 143 uint32_t buf_id; 144 }; 145 146 /* ------------------------------------------------------------------------- 147 * Data Structures - IOCTLs 148 * ------------------------------------------------------------------------- 149 */ 150 struct msm_npu_map_buf_ioctl { 151 /* buffer ion handle */ 152 int32_t buf_ion_hdl; 153 /* buffer size */ 154 uint32_t size; 155 /* iommu mapped physical address */ 156 uint64_t npu_phys_addr; 157 }; 158 159 struct msm_npu_unmap_buf_ioctl { 160 /* buffer ion handle */ 161 int32_t buf_ion_hdl; 162 /* iommu mapped physical address */ 163 uint64_t npu_phys_addr; 164 }; 165 166 struct msm_npu_get_info_ioctl { 167 /* firmware version */ 168 uint32_t firmware_version; 169 /* reserved */ 170 uint32_t flags; 171 }; 172 173 struct msm_npu_load_network_ioctl { 174 /* buffer ion handle */ 175 int32_t buf_ion_hdl; 176 /* physical address */ 177 uint64_t buf_phys_addr; 178 /* buffer size */ 179 uint32_t buf_size; 180 /* first block size */ 181 uint32_t first_block_size; 182 /* reserved */ 183 uint32_t flags; 184 /* network handle */ 185 uint32_t network_hdl; 186 /* priority */ 187 uint32_t priority; 188 /* perf mode */ 189 uint32_t perf_mode; 190 }; 191 192 struct msm_npu_load_network_ioctl_v2 { 193 /* physical address */ 194 uint64_t buf_phys_addr; 195 /* patch info(v2) for all input/output layers */ 196 uint64_t patch_info; 197 /* buffer ion handle */ 198 int32_t buf_ion_hdl; 199 /* buffer size */ 200 uint32_t buf_size; 201 /* first block size */ 202 uint32_t first_block_size; 203 /* load flags */ 204 uint32_t flags; 205 /* network handle */ 206 uint32_t network_hdl; 207 /* priority */ 208 uint32_t priority; 209 /* perf mode */ 210 uint32_t perf_mode; 211 /* number of layers in the network */ 212 uint32_t num_layers; 213 /* number of layers to be patched */ 214 uint32_t patch_info_num; 215 /* reserved */ 216 uint32_t reserved; 217 }; 218 219 struct msm_npu_unload_network_ioctl { 220 /* network handle */ 221 uint32_t network_hdl; 222 }; 223 224 struct msm_npu_exec_network_ioctl { 225 /* network handle */ 226 uint32_t network_hdl; 227 /* input layer number */ 228 uint32_t input_layer_num; 229 /* input layer info */ 230 struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM]; 231 /* output layer number */ 232 uint32_t output_layer_num; 233 /* output layer info */ 234 struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM]; 235 /* patching is required */ 236 uint32_t patching_required; 237 /* asynchronous execution */ 238 uint32_t async; 239 /* reserved */ 240 uint32_t flags; 241 }; 242 243 struct msm_npu_exec_network_ioctl_v2 { 244 /* stats buffer to be filled with execution stats */ 245 uint64_t stats_buf_addr; 246 /* patch buf info for both input and output layers */ 247 uint64_t patch_buf_info; 248 /* network handle */ 249 uint32_t network_hdl; 250 /* asynchronous execution */ 251 uint32_t async; 252 /* execution flags */ 253 uint32_t flags; 254 /* stats buf size allocated */ 255 uint32_t stats_buf_size; 256 /* number of layers to be patched */ 257 uint32_t patch_buf_info_num; 258 /* reserved */ 259 uint32_t reserved; 260 }; 261 262 struct msm_npu_event_execute_done { 263 uint32_t network_hdl; 264 int32_t exec_result; 265 }; 266 267 struct msm_npu_event_execute_v2_done { 268 uint32_t network_hdl; 269 int32_t exec_result; 270 /* stats buf size filled */ 271 uint32_t stats_buf_size; 272 }; 273 274 struct msm_npu_event_ssr { 275 uint32_t network_hdl; 276 }; 277 278 struct msm_npu_event { 279 uint32_t type; 280 union { 281 struct msm_npu_event_execute_done exec_done; 282 struct msm_npu_event_execute_v2_done exec_v2_done; 283 struct msm_npu_event_ssr ssr; 284 uint8_t data[128]; 285 } u; 286 uint32_t reserved[4]; 287 }; 288 289 struct msm_npu_property { 290 uint32_t prop_id; 291 uint32_t num_of_params; 292 uint32_t network_hdl; 293 uint32_t prop_param[PROP_PARAM_MAX_SIZE]; 294 }; 295 296 #endif /* _MSM_NPU_H_*/ 297