1 /* 2 * Copyright (C) 2023 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ANDROID_EXYNOS_HWC_MODULE_ZUMAPRO_H_ 18 #define ANDROID_EXYNOS_HWC_MODULE_ZUMAPRO_H_ 19 20 #include "../../zuma/libhwc2.1/ExynosHWCModule.h" 21 #include "ExynosHWCHelper.h" 22 23 namespace zumapro { 24 25 static const char *early_wakeup_node_0_base = 26 "/sys/devices/platform/19470000.drmdecon/early_wakeup"; 27 28 typedef enum assignOrderType { 29 ORDER_AFBC, 30 ORDER_WCG, 31 ORDER_AXI, 32 } assignOrderType_t; 33 34 typedef enum DPUblockId { 35 DPUF0, 36 DPUF1, 37 DPU_BLOCK_CNT, 38 } DPUblockId_t; 39 40 const std::unordered_map<DPUblockId_t, String8> DPUBlocks = { 41 {DPUF0, String8("DPUF0")}, 42 {DPUF1, String8("DPUF1")}, 43 }; 44 45 typedef enum AXIPortId { 46 AXI0, 47 AXI1, 48 AXI_PORT_MAX_CNT, 49 AXI_DONT_CARE 50 } AXIPortId_t; 51 52 const std::map<AXIPortId_t, String8> AXIPorts = { 53 {AXI0, String8("AXI0")}, 54 {AXI1, String8("AXI1")}, 55 }; 56 57 typedef enum ConstraintRev { 58 CONSTRAINT_NONE = 0, // don't care 59 CONSTRAINT_A0, 60 CONSTRAINT_B0 61 } ConstraintRev_t; 62 63 static const dpp_channel_map_t idma_channel_map[] = { 64 /* GF physical index is switched to change assign order */ 65 /* DECON_IDMA is not used */ 66 {MPP_DPP_GFS, 0, IDMA(0), IDMA(0)}, 67 {MPP_DPP_VGRFS, 0, IDMA(1), IDMA(1)}, 68 {MPP_DPP_GFS, 1, IDMA(2), IDMA(2)}, 69 {MPP_DPP_VGRFS, 1, IDMA(3), IDMA(3)}, 70 {MPP_DPP_GFS, 2, IDMA(4), IDMA(4)}, 71 {MPP_DPP_VGRFS, 2, IDMA(5), IDMA(5)}, 72 {MPP_DPP_GFS, 3, IDMA(6), IDMA(6)}, 73 {MPP_DPP_GFS, 4, IDMA(7), IDMA(7)}, 74 {MPP_DPP_VGRFS, 3, IDMA(8), IDMA(8)}, 75 {MPP_DPP_GFS, 5, IDMA(9), IDMA(9)}, 76 {MPP_DPP_VGRFS, 4, IDMA(10), IDMA(10)}, 77 {MPP_DPP_GFS, 6, IDMA(11), IDMA(11)}, 78 {MPP_DPP_VGRFS, 5, IDMA(12), IDMA(12)}, 79 {MPP_DPP_GFS, 7, IDMA(13), IDMA(13)}, 80 {MPP_P_TYPE_MAX, 0, ODMA_WB, IDMA(14)}, // not idma but.. 81 {static_cast<mpp_phycal_type_t>(MAX_DECON_DMA_TYPE), 0, MAX_DECON_DMA_TYPE, 82 IDMA(15)}}; 83 84 static const exynos_mpp_t available_otf_mpp_units[] = { 85 // There are total 14 layers(8 graphics-only and 6 video-graphics layers) 86 87 // DPP0(IDMA_GFS0) in DPUF0 is connected with AXI0 port 88 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 89 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 90 // DPP1(IDMA_VGRFS0) in DPUF0 is connected with AXI0 port 91 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 92 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 93 // DPP2(IDMA_GFS1) in DPUF0 is connected with AXI0 port 94 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 95 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 96 // DPP3(IDMA_VGRFS1) in DPUF0 is connected with AXI0 port 97 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 98 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)}, 99 100 // DPP4(IDMA_GFS2) in DPUF0 is connected with AXI1 port 101 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS2", 2, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 102 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)}, 103 // DPP5(IDMA_VGRFS2) in DPUF0 is connected with AXI1 port 104 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 105 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)}, 106 // DPP6(IDMA_GFS3) in DPUF0 is connected with AXI1 port 107 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS3", 3, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 108 static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)}, 109 110 // DPP7(IDMA_GFS4) in DPUF1 is connected with AXI1 port 111 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS4", 4, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 112 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 113 // DPP8(IDMA_VGRFS3) in DPUF1 is connected with AXI1 port 114 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS3", 3, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 115 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 116 // DPP9(IDMA_GFS5) in DPUF1 is connected with AXI1 port 117 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS5", 5, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 118 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 119 // DPP10(IDMA_VGRFS4) in DPUF1 is connected with AXI1 port 120 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS4", 4, 0, HWC_RESERVE_DISPLAY_MAIN_BIT, 121 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, 122 123 // DPP11(IDMA_GFS6) in DPUF1 is connected with AXI0 port 124 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 125 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, 126 // DPP12(IDMA_VGRFS5) in DPUF1 is connected with AXI0 port 127 {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS5", 5, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 128 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, 129 // DPP13(IDMA_GFS7) in DPUF1 is connected with AXI0 port 130 {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_RESERVE_DISPLAY_MINOR_BIT, 131 static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, 132 }; 133 134 static const std::array<exynos_display_t, 3> AVAILABLE_DISPLAY_UNITS = { 135 {{HWC_DISPLAY_PRIMARY, 0, "PrimaryDisplay", "/dev/dri/card0", ""}, 136 {HWC_DISPLAY_PRIMARY, 1, "SecondaryDisplay", "/dev/dri/card0", ""}, 137 {HWC_DISPLAY_EXTERNAL, 0, "ExternalDisplay", "/dev/dri/card0", ""}}}; 138 139 /* 140 * Note : 141 * When External or Virtual display is connected, 142 * Primary amount = total - others 143 */ 144 class HWResourceIndexes { 145 private: 146 tdm_attr_t attr; 147 DPUblockId_t DPUBlockNo; 148 AXIPortId_t axiId; 149 ConstraintRev_t constraintRev; 150 151 public: HWResourceIndexes(const tdm_attr_t & _attr,const DPUblockId_t & _DPUBlockNo,const AXIPortId_t & _axiId,const ConstraintRev_t & _constraintRev)152 HWResourceIndexes(const tdm_attr_t& _attr, const DPUblockId_t& _DPUBlockNo, 153 const AXIPortId_t& _axiId, const ConstraintRev_t& _constraintRev) 154 : attr(_attr), DPUBlockNo(_DPUBlockNo), axiId(_axiId), constraintRev(_constraintRev) {} 155 bool operator<(const HWResourceIndexes& rhs) const { 156 if (attr != rhs.attr) return attr < rhs.attr; 157 158 if (DPUBlockNo != rhs.DPUBlockNo) return DPUBlockNo < rhs.DPUBlockNo; 159 160 if (axiId != AXI_DONT_CARE && rhs.axiId != AXI_DONT_CARE && axiId != rhs.axiId) 161 return axiId < rhs.axiId; 162 163 if (constraintRev != CONSTRAINT_NONE) return constraintRev < rhs.constraintRev; 164 165 return false; 166 } toString8()167 String8 toString8() const { 168 String8 log; 169 log.appendFormat("attr=%d,DPUBlockNo=%d,axiId=%d,constraintRev=%d", attr, DPUBlockNo, axiId, 170 constraintRev); 171 return log; 172 } 173 }; 174 175 typedef struct HWResourceAmounts { 176 int mainAmount; 177 int minorAmount; 178 int total; 179 } HWResourceAmounts_t; 180 181 /* Note : 182 * When External or Virtual display is connected, 183 * Primary amount = total - others */ 184 185 const std::map<HWResourceIndexes, HWResourceAmounts_t> HWResourceTables = { 186 // SRAM 187 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {50, 30, 80}}, 188 {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {50, 30, 80}}, 189 // SCALE 190 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {2, 0, 2}}, 191 {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}}, 192 // SBWC 193 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {2, 0, 2}}, 194 {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {0, 2, 2}}, 195 // AFBC 196 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {3, 1, 4}}, 197 {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 3, 4}}, 198 // ITP 199 {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {3, 1, 4}}, 200 {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 3, 4}}, 201 // ROT_90 202 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}}, 203 {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}}, 204 // WCG 205 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, CONSTRAINT_A0), {2, 0, 2}}, 206 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, CONSTRAINT_A0), {0, 2, 2}}, 207 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, CONSTRAINT_B0), {2, 0, 2}}, 208 {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, CONSTRAINT_B0), {2, 0, 2}}, 209 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, CONSTRAINT_B0), {0, 2, 2}}, 210 {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, CONSTRAINT_B0), {0, 2, 2}}, 211 }; 212 213 typedef enum lbWidthIndex { 214 LB_W_8_512, 215 LB_W_513_1024, 216 LB_W_1025_1536, 217 LB_W_1537_2048, 218 LB_W_2049_2304, 219 LB_W_2305_2560, 220 LB_W_2561_3072, 221 LB_W_3073_INF, 222 } lbWidthIndex_t; 223 224 typedef struct lbWidthBoundary { 225 uint32_t widthDownto; 226 uint32_t widthUpto; 227 } lbWidthBoundary_t; 228 229 const std::map<lbWidthIndex_t, lbWidthBoundary_t> LB_WIDTH_INDEX_MAP = { 230 {LB_W_8_512, {8, 512}}, {LB_W_513_1024, {513, 1024}}, 231 {LB_W_1025_1536, {1025, 1536}}, {LB_W_1537_2048, {1537, 2048}}, 232 {LB_W_2049_2304, {2049, 2304}}, {LB_W_2305_2560, {2035, 2560}}, 233 {LB_W_2561_3072, {2561, 3072}}, {LB_W_3073_INF, {3073, 0xffff}}, 234 }; 235 236 class sramAmountParams { 237 private: 238 tdm_attr_t attr; 239 uint32_t formatProperty; 240 lbWidthIndex_t widthIndex; 241 242 public: sramAmountParams(tdm_attr_t _attr,uint32_t _formatProperty,lbWidthIndex_t _widthIndex)243 sramAmountParams(tdm_attr_t _attr, uint32_t _formatProperty, 244 lbWidthIndex_t _widthIndex) 245 : attr(_attr), formatProperty(_formatProperty), widthIndex(_widthIndex) {} 246 bool operator<(const sramAmountParams &rhs) const { 247 if (attr != rhs.attr) 248 return attr < rhs.attr; 249 250 if (formatProperty != rhs.formatProperty) 251 return formatProperty < rhs.formatProperty; 252 253 if (widthIndex != rhs.widthIndex) 254 return widthIndex < rhs.widthIndex; 255 256 return false; 257 } 258 }; 259 260 enum { 261 SBWC_Y = 0, 262 SBWC_UV, 263 NON_SBWC_Y, 264 NON_SBWC_UV, 265 }; 266 267 const std::map<sramAmountParams, uint32_t> sramAmountMap = { 268 /** Non rotation **/ 269 /** BIT8 = 32bit format **/ 270 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_8_512), 4}, 271 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_513_1024), 4}, 272 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_1025_1536), 8}, 273 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_1537_2048), 8}, 274 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2049_2304), 12}, 275 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2305_2560), 12}, 276 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_2561_3072), 12}, 277 {sramAmountParams(TDM_ATTR_AFBC, RGB | BIT8, LB_W_3073_INF), 16}, 278 279 /** 16bit format **/ 280 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_8_512), 2}, 281 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_513_1024), 2}, 282 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_1025_1536), 4}, 283 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_1537_2048), 4}, 284 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2049_2304), 6}, 285 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2305_2560), 6}, 286 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_2561_3072), 6}, 287 {sramAmountParams(TDM_ATTR_AFBC, RGB, LB_W_3073_INF), 8}, 288 289 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_8_512), 1}, 290 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_513_1024), 1}, 291 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_1025_1536), 1}, 292 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_1537_2048), 1}, 293 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2049_2304), 2}, 294 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2305_2560), 2}, 295 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_2561_3072), 2}, 296 {sramAmountParams(TDM_ATTR_SBWC, SBWC_Y, LB_W_3073_INF), 2}, 297 298 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_8_512), 2}, 299 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_513_1024), 2}, 300 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_1025_1536), 2}, 301 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_1537_2048), 2}, 302 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2049_2304), 2}, 303 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2305_2560), 2}, 304 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_2561_3072), 2}, 305 {sramAmountParams(TDM_ATTR_SBWC, SBWC_UV, LB_W_3073_INF), 2}, 306 307 /** Rotation **/ 308 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_8_512), 4}, 309 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_513_1024), 8}, 310 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_1025_1536), 12}, 311 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_1537_2048), 16}, 312 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2049_2304), 18}, 313 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2305_2560), 18}, 314 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_2561_3072), 18}, 315 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT8, LB_W_3073_INF), 18}, 316 317 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_8_512), 2}, 318 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_513_1024), 4}, 319 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_1025_1536), 6}, 320 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_1537_2048), 8}, 321 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2049_2304), 10}, 322 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2305_2560), 10}, 323 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_2561_3072), 10}, 324 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT8, LB_W_3073_INF), 10}, 325 326 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_8_512), 2}, 327 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_513_1024), 4}, 328 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_1025_1536), 6}, 329 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_1537_2048), 8}, 330 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2049_2304), 9}, 331 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2305_2560), 9}, 332 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_2561_3072), 9}, 333 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_Y | BIT10, LB_W_3073_INF), 9}, 334 335 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_8_512), 2}, 336 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_513_1024), 2}, 337 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_1025_1536), 4}, 338 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_1537_2048), 4}, 339 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2049_2304), 6}, 340 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2305_2560), 6}, 341 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_2561_3072), 6}, 342 {sramAmountParams(TDM_ATTR_ROT_90, NON_SBWC_UV | BIT10, LB_W_3073_INF), 6}, 343 344 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_8_512), 2}, 345 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_513_1024), 4}, 346 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_1025_1536), 6}, 347 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_1537_2048), 8}, 348 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2049_2304), 9}, 349 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2305_2560), 9}, 350 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_2561_3072), 9}, 351 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_Y, LB_W_3073_INF), 9}, 352 353 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_8_512), 2}, 354 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_513_1024), 2}, 355 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_1025_1536), 4}, 356 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_1537_2048), 4}, 357 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2049_2304), 6}, 358 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2305_2560), 6}, 359 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_2561_3072), 6}, 360 {sramAmountParams(TDM_ATTR_ROT_90, SBWC_UV, LB_W_3073_INF), 6}, 361 362 {sramAmountParams(TDM_ATTR_ITP, BIT8, LB_W_3073_INF), 2}, 363 {sramAmountParams(TDM_ATTR_ITP, BIT10, LB_W_3073_INF), 2}, 364 365 /* It's meaning like ow, 366 * FORMAT_YUV_MASK == has no alpha, FORMAT_RGB_MASK == has alpha */ 367 {sramAmountParams(TDM_ATTR_SCALE, FORMAT_YUV_MASK, LB_W_3073_INF), 12}, 368 {sramAmountParams(TDM_ATTR_SCALE, FORMAT_RGB_MASK, LB_W_3073_INF), 16}}; 369 } // namespace zumapro 370 371 #endif // ANDROID_EXYNOS_HWC_MODULE_ZUMAPRO_H_ 372