1 /*
2 * Copyright (c) 2015 Google Inc. All rights reserved
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <debug.h>
25 #include <dev/interrupt/arm_gic.h>
26 #include <dev/timer/arm_generic.h>
27 #include <inttypes.h>
28 #include <kernel/vm.h>
29 #include <lib/device_tree/libfdt_helpers.h>
30 #include <lk/init.h>
31 #include <platform/gic.h>
32 #include <string.h>
33 #include <sys/types.h>
34
35 #include "debug.h"
36
37 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
38 #include "smc.h"
39 #endif
40
41 #define ARM_GENERIC_TIMER_INT_CNTV 27
42 #define ARM_GENERIC_TIMER_INT_CNTPS 29
43 #define ARM_GENERIC_TIMER_INT_CNTP 30
44
45 #define ARM_GENERIC_TIMER_INT_SELECTED(timer) ARM_GENERIC_TIMER_INT_##timer
46 #define XARM_GENERIC_TIMER_INT_SELECTED(timer) \
47 ARM_GENERIC_TIMER_INT_SELECTED(timer)
48 #define ARM_GENERIC_TIMER_INT \
49 XARM_GENERIC_TIMER_INT_SELECTED(TIMER_ARM_GENERIC_SELECTED)
50
51 #if GIC_VERSION <= 2
52 #define GICC_SIZE (0x1000)
53 #define GICD_SIZE (0x1000)
54 #define GICR_SIZE (0)
55 #else
56 #define GICC_SIZE (0x10000)
57 #define GICD_SIZE (0x10000)
58 #if GIC_VERSION < 4
59 #define GICR_SIZE (0x20000 * SMP_MAX_CPUS)
60 #else
61 #define GICR_SIZE (0x40000 * SMP_MAX_CPUS)
62 #endif
63 #endif
64
65 extern ulong lk_boot_args[4];
66
67 #if ARM64_BOOT_PROTOCOL_X0_DTB
generic_arm64_reserve_device_tree(paddr_t ram_base,size_t ram_size)68 static void generic_arm64_reserve_device_tree(paddr_t ram_base,
69 size_t ram_size) {
70 struct list_node list;
71 list_initialize(&list);
72
73 paddr_t fdt_paddr = lk_boot_args[0];
74 if (fdt_paddr < ram_base || fdt_paddr - ram_base >= ram_size) {
75 /* fdt address is outside ram_arena, no need to reserve it */
76 return;
77 }
78 const void* fdt = paddr_to_kvaddr(fdt_paddr);
79 if (fdt_check_header(fdt)) {
80 return;
81 }
82 size_t fdt_size = fdt_totalsize(fdt);
83 /* if fdt_paddr is not page aligned add offset in first page to size */
84 fdt_size += fdt_paddr & (PAGE_SIZE - 1);
85 uint fdt_page_count = DIV_ROUND_UP(fdt_size, PAGE_SIZE);
86 uint fdt_reserved_page_count =
87 pmm_alloc_range(fdt_paddr, fdt_page_count, &list);
88 if (fdt_page_count != fdt_reserved_page_count) {
89 panic("failed to reserve memory for device tree");
90 }
91 }
92 #endif
93
94 /* initial memory mappings. parsed by start.S */
95 struct mmu_initial_mapping mmu_initial_mappings[] = {
96 /* Mark next entry as dynamic as it might be updated
97 by platform_reset code to specify actual size and
98 location of RAM to use */
99 {.phys = MEMBASE + KERNEL_LOAD_OFFSET,
100 .virt = KERNEL_BASE + KERNEL_LOAD_OFFSET,
101 .size = MEMSIZE,
102 .flags = MMU_INITIAL_MAPPING_FLAG_DYNAMIC,
103 .name = "ram"},
104
105 /* null entry to terminate the list */
106 {0, 0, 0, 0, 0}};
107
108 static pmm_arena_t ram_arena = {.name = "ram",
109 .base = MEMBASE + KERNEL_LOAD_OFFSET,
110 .size = MEMSIZE,
111 .flags = PMM_ARENA_FLAG_KMAP};
112
platform_init_mmu_mappings(void)113 void platform_init_mmu_mappings(void) {
114 /* go through mmu_initial_mapping to find dynamic entry
115 * matching ram_arena (by name) and adjust it.
116 */
117 struct mmu_initial_mapping* m = mmu_initial_mappings;
118 for (uint i = 0; i < countof(mmu_initial_mappings); i++, m++) {
119 if (!(m->flags & MMU_INITIAL_MAPPING_FLAG_DYNAMIC))
120 continue;
121
122 if (strcmp(m->name, ram_arena.name) == 0) {
123 /* update ram_arena */
124 ram_arena.base = m->phys;
125 ram_arena.size = m->size;
126 ram_arena.flags = PMM_ARENA_FLAG_KMAP;
127
128 break;
129 }
130 }
131 pmm_add_arena(&ram_arena);
132 #if ARM64_BOOT_PROTOCOL_X0_DTB
133 generic_arm64_reserve_device_tree(ram_arena.base, ram_arena.size);
134 #endif
135 }
136
137 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
138
generic_arm64_get_reg_base(int reg)139 static paddr_t generic_arm64_get_reg_base(int reg) {
140 #if ARCH_ARM64
141 return generic_arm64_smc(SMC_FC64_GET_REG_BASE, reg, 0, 0);
142 #else
143 return generic_arm64_smc(SMC_FC_GET_REG_BASE, reg, 0, 0);
144 #endif
145 }
146
147 #endif
148
platform_after_vm_init(uint level)149 static void platform_after_vm_init(uint level) {
150 #if ARM64_BOOT_PROTOCOL_X0_MEMSIZE || ARCH_ARM
151 paddr_t gicc = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICC);
152 paddr_t gicd = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICD);
153 paddr_t gicr = generic_arm64_get_reg_base(SMC_GET_GIC_BASE_GICR);
154 #elif ARM64_BOOT_PROTOCOL_X0_DTB
155 int ret;
156 void* fdt;
157 size_t fdt_size;
158 paddr_t fdt_paddr = lk_boot_args[0];
159 ret = vmm_alloc_physical(
160 vmm_get_kernel_aspace(), "device_tree_probe", PAGE_SIZE, &fdt, 0,
161 fdt_paddr, 0, ARCH_MMU_FLAG_PERM_NO_EXECUTE | ARCH_MMU_FLAG_CACHED);
162 if (ret) {
163 dprintf(CRITICAL,
164 "failed to map device tree page at 0x%" PRIxPADDR ": %d\n",
165 fdt_paddr, ret);
166 return;
167 }
168 if (fdt_check_header(fdt)) {
169 dprintf(CRITICAL, "invalid device tree at 0x%" PRIxPADDR ": %d\n",
170 fdt_paddr, ret);
171 return;
172 }
173 fdt_size = fdt_totalsize(fdt);
174 if (fdt_size > PAGE_SIZE) {
175 dprintf(INFO, "remapping device tree with size 0x%zx\n", fdt_size);
176 vmm_free_region(vmm_get_kernel_aspace(), (vaddr_t)fdt);
177 ret = vmm_alloc_physical(
178 vmm_get_kernel_aspace(), "device_tree_full", fdt_size, &fdt, 0,
179 fdt_paddr, 0,
180 ARCH_MMU_FLAG_PERM_NO_EXECUTE | ARCH_MMU_FLAG_CACHED);
181 if (ret) {
182 dprintf(CRITICAL,
183 "failed to map device tree at 0x%" PRIxPADDR
184 " sz 0x%zx: %d\n",
185 fdt_paddr, fdt_size, ret);
186 return;
187 }
188 }
189
190 generic_arm64_setup_uart(fdt);
191
192 int fdt_gic_offset = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
193 paddr_t gicc = 0; /* gic-v3 does not need a memory mapped gicc */
194 paddr_t gicd, gicr;
195 size_t gicd_size, gicr_size;
196 if (fdt_helper_get_reg(fdt, fdt_gic_offset, 0, &gicd, &gicd_size)) {
197 dprintf(CRITICAL, "failed get gicd regs, offset %d\n", fdt_gic_offset);
198 return;
199 }
200 if (fdt_helper_get_reg(fdt, fdt_gic_offset, 1, &gicr, &gicr_size)) {
201 dprintf(CRITICAL, "failed get gicr regs, offset %d\n", fdt_gic_offset);
202 return;
203 }
204 if (gicd_size != GICD_SIZE) {
205 dprintf(CRITICAL, "unexpected gicd_size %zd != %d\n", gicd_size,
206 GICD_SIZE);
207 return;
208 }
209 if (gicr_size < GICR_SIZE) {
210 dprintf(CRITICAL, "unexpected gicr_size %zd < %d\n", gicr_size,
211 GICR_SIZE);
212 return;
213 }
214 #else
215 #error "Unknown ARM64_BOOT_PROTOCOL"
216 #endif
217 dprintf(SPEW,
218 "gicc 0x%" PRIxPADDR ", gicd 0x%" PRIxPADDR ", gicr 0x%" PRIxPADDR
219 "\n",
220 gicc, gicd, gicr);
221
222 /* initialize the interrupt controller */
223 struct arm_gic_init_info init_info = {
224 .gicc_paddr = gicc,
225 .gicc_size = GICC_SIZE,
226 .gicd_paddr = gicd,
227 .gicd_size = GICD_SIZE,
228 .gicr_paddr = gicr,
229 .gicr_size = GICR_SIZE,
230 };
231 arm_gic_init_map(&init_info);
232
233 /* initialize the timer block */
234 arm_generic_timer_init(ARM_GENERIC_TIMER_INT, 0);
235 }
236
237 LK_INIT_HOOK(platform_after_vm, platform_after_vm_init, LK_INIT_LEVEL_VM + 1);
238